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411ecc50f4
Add patches to coreboot 4.15 to: - show ME status even when device is disable - fix PCIe RP hotplug on Librem 14 - fix ME reset timeout on Librem 13/15 This synchronizes with Purism's coreboot 4.15-Purism-3 tag. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
67 lines
2.2 KiB
Diff
67 lines
2.2 KiB
Diff
From 6d4b0be203b99e66043991796e1fdbbba26ba3ce Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Tue, 25 Jan 2022 12:41:49 -0600
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Subject: [PATCH 6/9] soc/intel/skylake: move heci_init() from bootblock to
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romstage
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Aligns with all other soc/intel/common platforms calling heci_init().
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Test: build/boot Purism Librem 13v2
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Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378
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Reviewed-by: Subrata Banik <subratabanik@google.com>
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Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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---
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src/soc/intel/skylake/bootblock/pch.c | 4 ----
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src/soc/intel/skylake/romstage/romstage.c | 3 +++
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2 files changed, 3 insertions(+), 4 deletions(-)
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diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
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index 1685e43e0e..ec60cabbea 100644
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--- a/src/soc/intel/skylake/bootblock/pch.c
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+++ b/src/soc/intel/skylake/bootblock/pch.c
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@@ -2,7 +2,6 @@
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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-#include <intelblocks/cse.h>
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#include <intelblocks/dmi.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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@@ -141,8 +140,5 @@ void bootblock_pch_init(void)
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enable_rtc_upper_bank();
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- /* initialize Heci interface */
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- heci_init(HECI1_BASE_ADDRESS);
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-
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gspi_early_bar_init();
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}
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diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
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index 30f65eae01..7e891b19f8 100644
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--- a/src/soc/intel/skylake/romstage/romstage.c
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+++ b/src/soc/intel/skylake/romstage/romstage.c
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@@ -4,6 +4,7 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <fsp/util.h>
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+#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/smbus.h>
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#include <memory_info.h>
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@@ -127,6 +128,8 @@ void mainboard_romstage_entry(void)
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systemagent_early_init();
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/* Program SMBus base address and enable it */
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smbus_common_init();
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+ /* initialize Heci interface */
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+ heci_init(HECI1_BASE_ADDRESS);
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ps = pmc_get_power_state();
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s3wake = pmc_fill_power_state(ps) == ACPI_S3;
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fsp_memory_init(s3wake);
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--
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2.30.2
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