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8bf187b50a
Add a new series of patches which add measurement support for skylake, add IOMMU for skylake, fix TPM support, and add support for TPM for the Librem 13v2 and Librem 15v3 hardware.
38 lines
1.1 KiB
Diff
38 lines
1.1 KiB
Diff
From 73c4fda90fdc4bd0bc6b383995d15b2c803cc274 Mon Sep 17 00:00:00 2001
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From: Youness Alaoui <youness.alaoui@puri.sm>
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Date: Fri, 2 Mar 2018 14:22:14 -0500
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Subject: [PATCH 13/15] intel/cpu: Fix SpeedStep enabling
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The IA32_MISC_ENABLE MSR was being overwritten by its old value
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right after enabling SpeedStep (eist) which caused it to revert
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the call to cpu_enable_eist().
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Fixes bug introduced in 6b45ee44.
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Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
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Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
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---
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src/soc/intel/skylake/cpu.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
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index 291a40da3e..d09a05667e 100644
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--- a/src/soc/intel/skylake/cpu.c
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+++ b/src/soc/intel/skylake/cpu.c
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@@ -260,11 +260,11 @@ static void configure_misc(void)
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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+ wrmsr(IA32_MISC_ENABLE, msr);
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if (conf->eist_enable)
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cpu_enable_eist();
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else
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cpu_disable_eist();
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- wrmsr(IA32_MISC_ENABLE, msr);
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/* Disable Thermal interrupts */
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msr.lo = 0;
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--
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2.14.3
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