heads/patches/coreboot-4.7/0013-intel-cpu-Fix-SpeedStep-enabling.patch
Youness Alaoui 8bf187b50a
Add patches to coreboot to support Librem 13 v2 with TPM
Add a new series of patches which add measurement support for skylake,
add IOMMU for skylake, fix TPM support, and add support for TPM for
the Librem 13v2 and Librem 15v3 hardware.
2018-03-14 16:27:25 -04:00

38 lines
1.1 KiB
Diff

From 73c4fda90fdc4bd0bc6b383995d15b2c803cc274 Mon Sep 17 00:00:00 2001
From: Youness Alaoui <youness.alaoui@puri.sm>
Date: Fri, 2 Mar 2018 14:22:14 -0500
Subject: [PATCH 13/15] intel/cpu: Fix SpeedStep enabling
The IA32_MISC_ENABLE MSR was being overwritten by its old value
right after enabling SpeedStep (eist) which caused it to revert
the call to cpu_enable_eist().
Fixes bug introduced in 6b45ee44.
Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
---
src/soc/intel/skylake/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 291a40da3e..d09a05667e 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -260,11 +260,11 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
if (conf->eist_enable)
cpu_enable_eist();
else
cpu_disable_eist();
- wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
msr.lo = 0;
--
2.14.3