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These two patches add the capability for coreboot to generate the RMRR ACPI tables needed for proper IOMMU support. These patches allow us to use 'intel_iommu=on' vs 'iommu=pt' Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
81 lines
3.3 KiB
Diff
81 lines
3.3 KiB
Diff
From 7267021c2a36ecd92aafdad2cae9ecab09e7e20d Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@gmail.com>
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Date: Mon, 25 Jun 2018 14:40:53 -0500
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Subject: [PATCH 3/3] soc/intel/skylake: Generate ACPI RMRR table
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An ACPI RMRR table is requried for IOMMU to work properly with an
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iGPU (without using passthrough mode), so create one along with the
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DRHD DMAR table if the iGPU is present and enabled.
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Test: build/boot google/chell and purism/librem13v2 with kernel
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parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated
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graphics functional without corruption.
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Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4
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Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
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Reviewed-on: https://review.coreboot.org/27270
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reviewed-by: Nico Huber <nico.h@gmx.de>
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Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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---
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.../common/block/include/intelblocks/systemagent.h | 2 ++
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.../intel/common/block/systemagent/systemagent_early.c | 2 +-
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src/soc/intel/skylake/acpi.c | 10 +++++++++-
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3 files changed, 12 insertions(+), 2 deletions(-)
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diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
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index a731b9cb0b..babf9cec95 100644
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--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
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+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
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@@ -77,6 +77,8 @@ void enable_power_aware_intr(void);
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uintptr_t sa_get_tolud_base(void);
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/* API to get DSM size */
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size_t sa_get_dsm_size(void);
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+/* API to get GSM base address */
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+uintptr_t sa_get_gsm_base(void);
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/* API to get GSM size */
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size_t sa_get_gsm_size(void);
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/* API to get TSEG base address */
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diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
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index 609e1596c9..c1cef5daf1 100644
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--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
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+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
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@@ -174,7 +174,7 @@ size_t sa_get_dsm_size(void)
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return (prealloc_memory - 0xEF) * 4*MiB;
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}
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-static uintptr_t sa_get_gsm_base(void)
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+uintptr_t sa_get_gsm_base(void)
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{
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/* All regions concerned for have 1 MiB alignment. */
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return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, BGSM), 1*MiB);
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diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
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index 760be590a3..eac9e0ac91 100644
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--- a/src/soc/intel/skylake/acpi.c
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+++ b/src/soc/intel/skylake/acpi.c
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@@ -548,12 +548,20 @@ static unsigned long acpi_fill_dmar(unsigned long current)
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/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
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if (igfx_dev && igfx_dev->enabled && gfxvten &&
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gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) {
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- const unsigned long tmp = current;
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+ unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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+
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+ /* Add RMRR entry */
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+ tmp = current;
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+
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+ current += acpi_create_dmar_rmrr(current, 0,
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+ sa_get_gsm_base(), sa_get_tolud_base() - 1);
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+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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+ acpi_dmar_rmrr_fixup(tmp, current);
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}
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struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
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--
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2.19.1
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