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16d9c405ac
Fixes access to the EC through the Index I/O interface Fixes AC and DC LoadLine values to avoid overheating problems Fix Turbo mode value from EC Change version name to have '-heads' suffix
195 lines
7.8 KiB
Diff
195 lines
7.8 KiB
Diff
From 7ac4919b8af16b62fb63592dbdd43ca9215c0cf7 Mon Sep 17 00:00:00 2001
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From: Youness Alaoui <youness.alaoui@puri.sm>
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Date: Tue, 20 Mar 2018 18:32:23 -0400
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Subject: [PATCH 3/3] purism/librem_skl: Add AC/DC LoadLine to VR Config
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The FSP 2.0 needs to set the ac_loadline and dc_loadline for
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each VR config. Without it, the Loadline is considered to be
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0 mOhm and this causes CPU temp to jump all over the place
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whenever the CPU is used.
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These values were copied from the Google Poppy devicetree.
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Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
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Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
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---
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.../librem_skl/variants/librem13v2/devicetree.cb | 40 ++++++++++++++--------
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.../librem_skl/variants/librem15v3/devicetree.cb | 40 ++++++++++++++--------
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2 files changed, 50 insertions(+), 30 deletions(-)
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diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
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index da97fb9ea7..a08a3df5f4 100644
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--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
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+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
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@@ -31,8 +31,8 @@ chip soc/intel/skylake
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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- # Enable DPTF
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- register "dptf_enable" = "1"
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+ # Disable DPTF
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+ register "dptf_enable" = "0"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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@@ -82,19 +82,21 @@ chip soc/intel/skylake
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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- #+----------------+-------+-------+-------------+-------+
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- #| Domain/Setting | SA | IA | GT Unsliced | GT |
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- #+----------------+-------+-------+-------------+-------+
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- #| Psi1Threshold | 20A | 20A | 20A | 20A |
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- #| Psi2Threshold | 4A | 5A | 5A | 5A |
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- #| Psi3Threshold | 1A | 1A | 1A | 1A |
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- #| Psi3Enable | 1 | 1 | 1 | 1 |
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- #| Psi4Enable | 1 | 1 | 1 | 1 |
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- #| ImonSlope | 0 | 0 | 0 | 0 |
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- #| ImonOffset | 0 | 0 | 0 | 0 |
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- #| IccMax | 7A | 34A | 35A | 35A |
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- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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- #+----------------+-------+-------+-------------+-------+
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+ #+----------------+-----------+-----------+-------------+----------+
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+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
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+ #+----------------+-----------+-----------+-------------+----------+
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+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
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+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
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+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
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+ #| Psi3Enable | 1 | 1 | 1 | 1 |
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+ #| Psi4Enable | 1 | 1 | 1 | 1 |
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+ #| ImonSlope | 0 | 0 | 0 | 0 |
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+ #| ImonOffset | 0 | 0 | 0 | 0 |
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+ #| IccMax | 7A | 34A | 35A | 35A |
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+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
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+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
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+ #+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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@@ -106,6 +108,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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+ .ac_loadline = 1500,
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+ .dc_loadline = 1430,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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@@ -119,6 +123,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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+ .ac_loadline = 570,
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+ .dc_loadline = 483,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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@@ -132,6 +138,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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+ .ac_loadline = 520,
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+ .dc_loadline = 420,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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@@ -145,6 +153,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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+ .ac_loadline = 520,
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+ .dc_loadline = 420,
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}"
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# Enable Root Ports 5 and 9
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diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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index deaf3a6deb..7dff719096 100644
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--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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@@ -31,8 +31,8 @@ chip soc/intel/skylake
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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- # Enable DPTF
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- register "dptf_enable" = "1"
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+ # Disable DPTF
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+ register "dptf_enable" = "0"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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@@ -82,19 +82,21 @@ chip soc/intel/skylake
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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- #+----------------+-------+-------+-------------+-------+
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- #| Domain/Setting | SA | IA | GT Unsliced | GT |
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- #+----------------+-------+-------+-------------+-------+
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- #| Psi1Threshold | 20A | 20A | 20A | 20A |
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- #| Psi2Threshold | 4A | 5A | 5A | 5A |
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- #| Psi3Threshold | 1A | 1A | 1A | 1A |
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- #| Psi3Enable | 1 | 1 | 1 | 1 |
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- #| Psi4Enable | 1 | 1 | 1 | 1 |
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- #| ImonSlope | 0 | 0 | 0 | 0 |
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- #| ImonOffset | 0 | 0 | 0 | 0 |
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- #| IccMax | 7A | 34A | 35A | 35A |
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- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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- #+----------------+-------+-------+-------------+-------+
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+ #+----------------+-----------+-----------+-------------+----------+
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+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
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+ #+----------------+-----------+-----------+-------------+----------+
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+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
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+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
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+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
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+ #| Psi3Enable | 1 | 1 | 1 | 1 |
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+ #| Psi4Enable | 1 | 1 | 1 | 1 |
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+ #| ImonSlope | 0 | 0 | 0 | 0 |
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+ #| ImonOffset | 0 | 0 | 0 | 0 |
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+ #| IccMax | 7A | 34A | 35A | 35A |
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+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
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+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
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+ #+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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@@ -106,6 +108,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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+ .ac_loadline = 1500,
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+ .dc_loadline = 1430,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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@@ -119,6 +123,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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+ .ac_loadline = 570,
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+ .dc_loadline = 483,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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@@ -132,6 +138,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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+ .ac_loadline = 520,
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+ .dc_loadline = 420,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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@@ -145,6 +153,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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+ .ac_loadline = 520,
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+ .dc_loadline = 420,
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}"
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# Enable Root Ports 5 and 9
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--
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2.14.3
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