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The added patches fix bugs in fam15h ram DQS timing and configure the motherboard to restart gracefully if raminit fails instead of booting into an unstable state and/or crashing. Signed-off-by: Thierry Laurion <insurgo@riseup.net>
63 lines
2.3 KiB
Diff
63 lines
2.3 KiB
Diff
From f6c818898b3f978bd22ed2829a881322e0eadaf9 Mon Sep 17 00:00:00 2001
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From: Mike Rothfuss <6182328+mrothfuss@users.noreply.github.com>
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Date: Fri, 23 Aug 2024 19:54:54 -0600
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Subject: [PATCH 1/2] northbridge/amd: Fixed errors in fam15h DQS timing
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Fixed two errors in determining whether valid values were
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found for read DQS delays in raminit.
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---
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src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 17 ++++++-----------
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1 file changed, 6 insertions(+), 11 deletions(-)
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diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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index d34b2dc2ba..6cf67afa4f 100644
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--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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@@ -21,6 +21,7 @@
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#include <arch/cpu.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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+#include <southbridge/amd/common/reset.h>
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#include "mct_d.h"
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#include "mct_d_gcc.h"
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@@ -1287,6 +1288,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
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uint8_t cur_count = 0;
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uint8_t best_pos = 0;
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uint8_t best_count = 0;
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+ uint16_t region_center;
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uint32_t index_reg = 0x98;
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uint32_t dev = pDCTstat->dev_dct;
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@@ -1455,23 +1457,16 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
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last_pos = 0;
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}
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- if (best_count > 2) {
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- uint16_t region_center = (best_pos + (best_count / 2));
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-
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- if (region_center < 16) {
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- printk(BIOS_WARNING, "TrainDQSRdWrPos: negative DQS recovery delay detected!"
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- " Attempting to continue but your system may be unstable...\n");
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- region_center = 0;
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- } else {
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- region_center -= 16;
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- }
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+ region_center = (best_pos + (best_count / 2));
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+ if ((best_count > 2) && (region_center >= 16)) {
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+ region_center -= 16;
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/* Restore current settings of other (previously trained) lanes to the active array */
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memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
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/* Program the Read DQS Timing Control register with the center of the passing window */
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current_read_dqs_delay[lane] = region_center;
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- passing_dqs_delay_found[lane] = 1;
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+ passing_read_dqs_delay_found = 1;
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/* Commit the current Read DQS Timing Control settings to the hardware registers */
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write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg);
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--
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2.39.2
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