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https://github.com/linuxboot/heads.git
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572f5b3414
cp config/linux.. ./build/linux*/.config cd build/linux* make savedefconfig cp defconfig ../../config/linux.. Resulting in only linux-kgpe-d16_workstation.config being updated. For KGPE-D16 workstation boards: Remove `console=tty0` from `CONFIG_BOOT_KERNEL_ADD` as was blocking Qubes graphical installer (CLI installer was launched). Comment out `export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"` to provide a more desktop like experience. Removed 0001-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch as already exists as 0000-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch Added 0020-kgpe-d16_measured-boot-support.patch for coreboot 4.11 Fix TPM errors when microcode is measured by initialising TPM earlier and loading the microcode later. Thanks to Michał Żygowski <miczyg1> for condition suggestion: `if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM) && boot_cpu())` Locate bootblock location and size with CBFS API. Credit to: Michał Żygowski <miczyg1>
68 lines
2.0 KiB
Diff
68 lines
2.0 KiB
Diff
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
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index 637ec42109..8a92f88375 100644
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--- a/src/mainboard/asus/kgpe-d16/romstage.c
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+++ b/src/mainboard/asus/kgpe-d16/romstage.c
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@@ -46,6 +46,12 @@
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#include <cbmem.h>
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#include <types.h>
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+#include <security/tpm/tss.h>
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+#include <security/tpm/tspi.h>
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+#include <program_loading.h>
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+#include <smp/node.h>
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+#include <cbfs.h>
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+
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#include "cpu/amd/quadcore/quadcore.c"
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#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
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@@ -547,7 +553,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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power_on_reset = 1;
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initialize_mca(1, power_on_reset);
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- update_microcode(val);
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post_code(0x33);
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@@ -573,6 +578,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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sr5650_early_setup();
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sb7xx_51xx_early_setup();
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+ if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM) && boot_cpu()) {
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+ tpm_setup(0);
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+ tlcl_lib_init();
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+ }
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+
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+ update_microcode(val);
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+
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if (CONFIG(LOGICAL_CPUS)) {
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/* Core0 on each node is configured. Now setup any additional cores. */
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printk(BIOS_DEBUG, "start_other_cores()\n");
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@@ -687,6 +699,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
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pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
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pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
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+
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+ if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM)) {
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+ size_t bootblock_size = 0;
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+ const void *bootblock = cbfs_boot_map_with_leak("bootblock", 1, &bootblock_size);
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+ tlcl_measure(2, bootblock, bootblock_size);
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+
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+ extern char _romstage, _eromstage;
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+ tlcl_measure(2, &_romstage, &_eromstage - &_romstage);
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+ }
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+
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+
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}
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/**
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@@ -718,3 +741,9 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
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return 0;
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}
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+
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+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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+{
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+ if (CONFIG(MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
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+ tlcl_measure(2, (const void *) start, size);
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+}
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