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44 lines
1.9 KiB
Diff
44 lines
1.9 KiB
Diff
From 8e7e0e390fcfda226f0d78bfa883ffee12f751a8 Mon Sep 17 00:00:00 2001
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From: Youness Alaoui <youness.alaoui@puri.sm>
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Date: Fri, 9 Feb 2018 18:32:51 -0500
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Subject: [PATCH 7/9] intel/fsp/fsp2_0: Fix FSP 2.0 headers to match github
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version
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The current FSP 2.0 headers do not match the headers from the official
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FSP 2.0 image that was released on github [1].
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[1] https://github.com/IntelFsp/FSP/tree/Kabylake/KabylakeFspBinPkg
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Change-Id: I233bf7cf6f62e9e1b389d42a09461717a3285f0f
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Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
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---
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src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h | 5 +----
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1 file changed, 1 insertion(+), 4 deletions(-)
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diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
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index 248b4d5ef1..3abc877a19 100644
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--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
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+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
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@@ -207,10 +207,6 @@ typedef struct {
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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- MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
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- MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
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- MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
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- MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
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} CONTROLLER_INFO;
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typedef struct {
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@@ -228,6 +224,7 @@ typedef struct {
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UINT8 ErrorCorrectionType;
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SiMrcVersion Version;
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+ UINT32 FreqMax;
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BOOLEAN EccSupport;
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UINT8 MemoryProfile;
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UINT32 TotalPhysicalMemorySize;
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--
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2.14.3
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