From 920c2e7fc2ba2a0bbe820e2f397e22bd92b0180d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 29 Oct 2020 20:37:56 -0500 Subject: [PATCH] mb/purism/librem_cnl: Adjust in preparation for new variants sync librem_cnl with coreboot upstream in preparation for addition of new Librem Mini v2 board Change-Id: Ic19bf6083557cedc96679a3f77187d75fecc4f0e Signed-off-by: Matt DeVillier --- src/mainboard/purism/librem_cnl/Kconfig | 10 +- src/mainboard/purism/librem_cnl/Kconfig.name | 1 + src/mainboard/purism/librem_cnl/Makefile.inc | 3 - .../purism/librem_cnl/acpi/mainboard.asl | 4 +- .../purism/librem_cnl/board_info.txt | 4 +- src/mainboard/purism/librem_cnl/devicetree.cb | 223 ----- src/mainboard/purism/librem_cnl/ramstage.c | 3 - src/mainboard/purism/librem_cnl/romstage.c | 9 +- .../variants/librem_mini/board_info.txt | 8 + .../variants/librem_mini/devicetree.cb | 252 ++++++ .../librem_cnl/variants/librem_mini/gpio.c | 796 +++++++++++++----- 11 files changed, 861 insertions(+), 452 deletions(-) delete mode 100644 src/mainboard/purism/librem_cnl/devicetree.cb create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 453490b7d2..464350ce8c 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -2,13 +2,13 @@ config BOARD_PURISM_BASEBOARD_LIBREM_CNL def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL + select DRIVERS_USB_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_WHISKEYLAKE select SPD_READ_BY_WORD select USE_LEGACY_8254_TIMER @@ -30,9 +30,13 @@ config VARIANT_DIR string default "librem_mini" if BOARD_PURISM_LIBREM_MINI +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config CBFS_SIZE hex - default 0x800000 + default 0x800000 if BOARD_PURISM_LIBREM_MINI config MAX_CPUS int @@ -48,7 +52,7 @@ config DIMM_SPD_SIZE config VGA_BIOS_ID string - default "8086,3ea0" + default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI config PXE_ROM_ID string diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name index 326165ba07..83f1495ab1 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig.name +++ b/src/mainboard/purism/librem_cnl/Kconfig.name @@ -1,3 +1,4 @@ config BOARD_PURISM_LIBREM_MINI bool "Librem Mini" select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select SOC_INTEL_WHISKEYLAKE diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc index c03db05423..ba157dfd05 100644 --- a/src/mainboard/purism/librem_cnl/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/Makefile.inc @@ -1,6 +1,3 @@ -## -## -## ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/purism/librem_cnl/acpi/mainboard.asl b/src/mainboard/purism/librem_cnl/acpi/mainboard.asl index 999030d2e5..0c9a76b168 100644 --- a/src/mainboard/purism/librem_cnl/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_cnl/acpi/mainboard.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope (\_SB.PCI0.LPCB) { - +Scope (\_SB.PCI0.LPCB) +{ Device (AC) { Name (_HID, "ACPI0003") diff --git a/src/mainboard/purism/librem_cnl/board_info.txt b/src/mainboard/purism/librem_cnl/board_info.txt index ca61edd88d..6c7620ce1e 100644 --- a/src/mainboard/purism/librem_cnl/board_info.txt +++ b/src/mainboard/purism/librem_cnl/board_info.txt @@ -1,6 +1,6 @@ Vendor name: Purism -Board name: librem_cnl -Category: desktop +Board name: Librem Cannonlake baseboard +Category: misc Release year: 2020 ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb deleted file mode 100644 index e67d910322..0000000000 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ /dev/null @@ -1,223 +0,0 @@ -chip soc/intel/cannonlake - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - -# ACPI (soc/intel/cannonlake/acpi.c) - # Disable s0ix - register "s0ix_enable" = "0" - - # PM Timer Enabled - register "PmTimerDisabled" = "0" - - # Disable DPTF - register "dptf_enable" = "0" - -# CPU (soc/intel/cannonlake/cpu.c) - # Power limit - register "tdp_pl1_override" = "15" - register "tdp_pl2_override" = "25" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - -# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" - -# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # SATA - register "SataMode" = "Sata_AHCI" - register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" - - # Audio - register "PchHdaDspEnable" = "0" - register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "0" - register "PchHdaAudioLinkDmic1" = "0" - register "PchHdaAudioLinkSsp0" = "0" - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkSsp2" = "0" - register "PchHdaAudioLinkSndw1" = "0" - register "PchHdaAudioLinkSndw2" = "0" - register "PchHdaAudioLinkSndw3" = "0" - register "PchHdaAudioLinkSndw4" = "0" - - # USB - register "SsicPortEnable" = "0" - - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper - register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC - register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC - register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC - register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC - - # All SRCCLKREQ pins mapped directly - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Set all SRCCLKREQ pins as free-use - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "0x80" - register "PcieClkSrcUsage[2]" = "0x80" - register "PcieClkSrcUsage[3]" = "0x80" - register "PcieClkSrcUsage[4]" = "0x80" - register "PcieClkSrcUsage[5]" = "0x80" - - # PCI Express Root Port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - - # PCI Express Root Port #10 x1, Clock 3 (LAN) - register "PcieRpEnable[9]" = "1" - register "PcieRpLtrEnable[9]" = "0" - - # PCI Express Root port #13 x4, Clock 1 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - - # Misc - register "Device4Enable" = "1" - # HECI must be enabled w/HAP disable else S3 issues - register "HeciEnabled" = "1" - register "Heci3Enabled" = "0" - register "AcousticNoiseMitigation" = "1" - register "satapwroptimize" = "1" - - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s - - # Thermal - register "tcc_offset" = "12" - - # Serial IRQ Mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - -# PMC (soc/intel/cannonlake/pmc.c) - # Disable deep Sx states - register "deep_sx_config" = "0" - -# PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" - -# Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 (WLAN) - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 (LAN) - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (NVMe) - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC Bridge - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/purism/librem_cnl/ramstage.c b/src/mainboard/purism/librem_cnl/ramstage.c index 3479c0d3ed..56ed1b7844 100644 --- a/src/mainboard/purism/librem_cnl/ramstage.c +++ b/src/mainboard/purism/librem_cnl/ramstage.c @@ -10,7 +10,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) size_t num_gpios; const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Limit SATA speed to 3Gbps */ - params->SataSpeedLimit = 2; } diff --git a/src/mainboard/purism/librem_cnl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c index 9f8d600950..3a3ca6b491 100644 --- a/src/mainboard/purism/librem_cnl/romstage.c +++ b/src/mainboard/purism/librem_cnl/romstage.c @@ -48,5 +48,12 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; } diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt b/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt new file mode 100644 index 0000000000..843ff9ff7c --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem Mini +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb new file mode 100644 index 0000000000..78236c7ea4 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -0,0 +1,252 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_FixedHigh" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.5 on end + end + end + end + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off # Management Engine Interface 1 + # HECI must be enabled w/HAP disable else S3 issues + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off # Management Engine Interface 3 + register "Heci3Enabled" = "0" + end + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "satapwroptimize" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 M.2/E 2230 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC + register "PcieClkSrcUsage[2]" = "0x80" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" + end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN) + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[3]" = "9" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Bridge + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index a5b2dcafa3..8fa4ac57ec 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -2,224 +2,590 @@ #include -/* Pad configuration in ramstage. */ +/* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { -/* ------- GPIO Group GPP_A ------- */ - -_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0000), /* RCIN# */ -_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ -_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ -_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ -_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ -_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0000), /* LFRAME# */ -_PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0000), /* SERIRQ */ -_PAD_CFG_STRUCT(GPP_A7, 0x84000200, 0x0000), /* PIRQA# */ -_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0000), /* CLKRUN# */ -_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ -_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ -_PAD_CFG_STRUCT(GPP_A11, 0x40880201, 0x0000), /* PME# */ -_PAD_CFG_STRUCT(GPP_A12, 0x84000201, 0x0000), /* BM_BUSY# */ -_PAD_CFG_STRUCT(GPP_A13, 0x84000201, 0x0000), /* SUSWARN#/SUSPWRDNACK*/ -_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0000), /* SUS_STAT# */ -_PAD_CFG_STRUCT(GPP_A15, 0x84000201, 0x0000), /* SUSACK# */ -_PAD_CFG_STRUCT(GPP_A16, 0x84000200, 0x3000), /* SD_1P8_SEL */ -_PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0000), /* SD_VDD1_PWR_EN# */ -_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x3000), /* ISH_GP0 */ -_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x3000), /* ISH_GP1 */ -_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x3000), /* ISH_GP2 */ -_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x3000), /* ISH_GP3 */ -_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x3000), /* ISH_GP4 */ -_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x3000), /* ISH_GP5 */ - -/* ------- GPIO Group GPP_B ------- */ - -_PAD_CFG_STRUCT(GPP_B0, 0x84000700, 0x0000), /* Reserved */ -_PAD_CFG_STRUCT(GPP_B1, 0x84000700, 0x0000), /* Reserved */ -_PAD_CFG_STRUCT(GPP_B2, 0x84000201, 0x0000), /* VRALERT# */ -_PAD_CFG_STRUCT(GPP_B3, 0x84000201, 0x0000), /* CPU_GP2 */ -_PAD_CFG_STRUCT(GPP_B4, 0x84000201, 0x0000), /* CPU_GP3 */ -_PAD_CFG_STRUCT(GPP_B5, 0x44000300, 0x0000), /* SRCCLKREQ0# */ -_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x0000), /* SRCCLKREQ1# */ -_PAD_CFG_STRUCT(GPP_B7, 0x44000300, 0x0000), /* SRCCLKREQ2# */ -_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0000), /* SRCCLKREQ3# */ -_PAD_CFG_STRUCT(GPP_B9, 0x44000300, 0x0000), /* SRCCLKREQ4# */ -_PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0000), /* SRCCLKREQ5# */ -_PAD_CFG_STRUCT(GPP_B11, 0x84000201, 0x0000), /* EXT_PWR_GATE# */ -_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0000), /* SLP_S0# */ -_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0000), /* PLTRST# */ -_PAD_CFG_STRUCT(GPP_B14, 0x84000201, 0x0000), /* SPKR */ -_PAD_CFG_STRUCT(GPP_B15, 0x80000701, 0x0000), /* GSPI0_CS0# */ -_PAD_CFG_STRUCT(GPP_B16, 0x84000601, 0x0000), /* GSPI0_CLK */ -_PAD_CFG_STRUCT(GPP_B17, 0x44000502, 0x0000), /* GSPI0_MISO */ -_PAD_CFG_STRUCT(GPP_B18, 0x84000601, 0x0000), /* GSPI0_MOSI */ -_PAD_CFG_STRUCT(GPP_B19, 0x84000400, 0x0000), /* GSPI1_CS0# */ -_PAD_CFG_STRUCT(GPP_B20, 0x84000400, 0x0000), /* GSPI1_CLK */ -_PAD_CFG_STRUCT(GPP_B21, 0x84000402, 0x0000), /* GSPI1_MISO */ -_PAD_CFG_STRUCT(GPP_B22, 0x84000400, 0x0000), /* GSPI1_MOSI */ -_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x0000), /* SML1ALERT# */ - -/* ------- GPIO Group GPP_G ------- */ - -_PAD_CFG_STRUCT(GPP_G0, 0x84000200, 0x0000), /* SD_CMD */ -_PAD_CFG_STRUCT(GPP_G1, 0x84000300, 0x0000), /* SD_DATA0 */ -_PAD_CFG_STRUCT(GPP_G2, 0x84000300, 0x0000), /* SD_DATA1 */ -_PAD_CFG_STRUCT(GPP_G3, 0x84000300, 0x0000), /* SD_DATA2 */ -_PAD_CFG_STRUCT(GPP_G4, 0x84000300, 0x0000), /* SD_DATA3 */ -_PAD_CFG_STRUCT(GPP_G5, 0x84000300, 0x3000), /* SD3_CD# */ -_PAD_CFG_STRUCT(GPP_G6, 0x84000300, 0x0000), /* SD3_CLK */ -_PAD_CFG_STRUCT(GPP_G7, 0x84000300, 0x1000), /* SD3_WP */ - -/* ------- GPIO Group GPP_D ------- */ - -_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x0000), /* SPI1_CS# */ -_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x0000), /* SPI1_CLK */ -_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x0000), /* SPI1_MISO */ -_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x0000), /* SPI1_MOSI */ -_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x0000), /* IMGCLKOUT0 */ -_PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0000), /* ISH_I2C0_SDA */ -_PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0000), /* ISH_I2C0_SCL */ -_PAD_CFG_STRUCT(GPP_D7, 0x84000201, 0x0000), /* ISH_I2C1_SDA */ -_PAD_CFG_STRUCT(GPP_D8, 0x84000200, 0x0000), /* ISH_I2C1_SCL */ -_PAD_CFG_STRUCT(GPP_D9, 0x84000201, 0x0000), /* ISH_SPI_CS# */ -_PAD_CFG_STRUCT(GPP_D10, 0x84000201, 0x0000), /* ISH_SPI_CLK */ -_PAD_CFG_STRUCT(GPP_D11, 0x44000201, 0x3000), /* ISH_SPI_MISO */ -_PAD_CFG_STRUCT(GPP_D12, 0x42100102, 0x3000), /* ISH_SPI_MOSI */ -_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x0000), /* ISH_UART0_RXD */ -_PAD_CFG_STRUCT(GPP_D14, 0x84000201, 0x0000), /* ISH_UART0_TXD */ -_PAD_CFG_STRUCT(GPP_D15, 0x84000201, 0x0000), /* ISH_UART0_RTS# */ -_PAD_CFG_STRUCT(GPP_D16, 0x44000200, 0x0000), /* ISH_UART0_CTS# */ -_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0000), /* DMIC_CLK1 */ -_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0000), /* DMIC_DATA1 */ -_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0000), /* DMIC_CLK0 */ -_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0000), /* DMIC_DATA0 */ -_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0000), /* SPI1_IO2 */ -_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0000), /* SPI1_IO3 */ -_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0000), /* I2S_MCLK */ - -/* ------- GPIO Group GPP_F ------- */ - -_PAD_CFG_STRUCT(GPP_F0, 0x84000301, 0x0000), /* CNV_PA_BLANKING */ -_PAD_CFG_STRUCT(GPP_F1, 0x84000200, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_F2, 0x84000201, 0x3000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_F3, 0x84000200, 0x3000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x3000), /* CNV_BRI_DT */ -_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x3000), /* CNV_BRI_RSP */ -_PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x3000), /* CNV_RGI_DT */ -_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x3000), /* CNV_RGI_RSP */ -_PAD_CFG_STRUCT(GPP_F8, 0x44000300, 0x0000), /* CNV_MFUART2_RXD */ -_PAD_CFG_STRUCT(GPP_F9, 0x44000300, 0x0000), /* CNV_MFUART2_TXD */ -_PAD_CFG_STRUCT(GPP_F10, 0x84000201, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0000), /* EMMC_CMD */ -_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0000), /* EMMC_DATA0 */ -_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0000), /* EMMC_DATA1 */ -_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x0000), /* EMMC_DATA2 */ -_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x0000), /* EMMC_DATA3 */ -_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x0000), /* EMMC_DATA4 */ -_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x0000), /* EMMC_DATA5 */ -_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x0000), /* EMMC_DATA6 */ -_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x0000), /* EMMC_DATA7 */ -_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x0000), /* EMMC_RCLK */ -_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x0000), /* EMMC_CLK */ -_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0000), /* EMMC_RESET# */ -_PAD_CFG_STRUCT(GPP_F23, 0x44000700, 0x1000), /* A4WP_PRESENT */ - -/* ------- GPIO Group GPP_H ------- */ - -_PAD_CFG_STRUCT(GPP_H0, 0x44000300, 0x3000), /* I2S2_SCLK */ -_PAD_CFG_STRUCT(GPP_H1, 0x44000f00, 0x3000), /* CNV_RF_RESET# */ -_PAD_CFG_STRUCT(GPP_H2, 0x84000f00, 0x3000), /* MODEM_CLKREQ */ -_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x3000), /* I2S2_RXD */ -_PAD_CFG_STRUCT(GPP_H4, 0x84000300, 0x0000), /* I2C2_SDA */ -_PAD_CFG_STRUCT(GPP_H5, 0x84000300, 0x0000), /* I2C2_SCL */ -_PAD_CFG_STRUCT(GPP_H6, 0x84000702, 0x0000), /* I2C3_SDA */ -_PAD_CFG_STRUCT(GPP_H7, 0x84000702, 0x0000), /* I2C3_SCL */ -_PAD_CFG_STRUCT(GPP_H8, 0x84000702, 0x0000), /* I2C4_SDA */ -_PAD_CFG_STRUCT(GPP_H9, 0x84000702, 0x0000), /* I2C4_SCL */ -_PAD_CFG_STRUCT(GPP_H10, 0x84000603, 0x0000), /* I2C5_SDA */ -_PAD_CFG_STRUCT(GPP_H11, 0x84000603, 0x0000), /* I2C5_SCL */ -_PAD_CFG_STRUCT(GPP_H12, 0x84000201, 0x0000), /* M2_SKT2_CFG0 */ -_PAD_CFG_STRUCT(GPP_H13, 0x84000201, 0x0000), /* M2_SKT2_CFG1 */ -_PAD_CFG_STRUCT(GPP_H14, 0x84000200, 0x0000), /* M2_SKT2_CFG2 */ -_PAD_CFG_STRUCT(GPP_H15, 0x84000201, 0x0000), /* M2_SKT2_CFG3 */ -_PAD_CFG_STRUCT(GPP_H16, 0x84000201, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_H17, 0x84000201, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_H18, 0x84000700, 0x0000), /* CPU_C10_GATE# */ -_PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x0000), /* TIME_SYNC0 */ -_PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000), /* IMGCLKOUT1 */ -_PAD_CFG_STRUCT(GPP_H21, 0x84000200, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_H23, 0x84000200, 0x0000), /* GPIO */ - -/* ------- GPIO Group GPD ------- */ - -_PAD_CFG_STRUCT(GPD0, 0x44000702, 0x0000), /* BATLOW# */ -_PAD_CFG_STRUCT(GPD1, 0x44000702, 0x3c00), /* ACPRESENT */ -_PAD_CFG_STRUCT(GPD2, 0x44000702, 0x3c00), /* LAN_WAKE# */ -_PAD_CFG_STRUCT(GPD3, 0x44000702, 0x3000), /* PRWBTN# */ -_PAD_CFG_STRUCT(GPD4, 0x44000600, 0x0000), /* SLP_S3# */ -_PAD_CFG_STRUCT(GPD5, 0x44000600, 0x0000), /* SLP_S4# */ -_PAD_CFG_STRUCT(GPD6, 0x44000600, 0x0000), /* SLP_A# */ -_PAD_CFG_STRUCT(GPD7, 0x44000200, 0x0000), /* GPIO */ -_PAD_CFG_STRUCT(GPD8, 0x44000700, 0x0000), /* SUSCLK */ -_PAD_CFG_STRUCT(GPD9, 0x44000700, 0x0000), /* SLP_WLAN# */ -_PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0000), /* SLP_S5# */ -_PAD_CFG_STRUCT(GPD11, 0x44000600, 0x0000), /* LANPHYPC */ - -/* ------- GPIO Group GPP_C ------- */ - -_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0000), /* SMBCLK */ -_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x0000), /* SMBDATA */ -_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x0000), /* SMBALERT# */ -_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0000), /* SML0CLK */ -_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0000), /* SML0DATA */ -_PAD_CFG_STRUCT(GPP_C5, 0x84000201, 0x0000), /* SML0ALERT# */ -_PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x0000), /* SML1CLK */ -_PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x0000), /* SML1DATA */ -_PAD_CFG_STRUCT(GPP_C8, 0x84000201, 0x0000), /* UART0_RXD */ -_PAD_CFG_STRUCT(GPP_C9, 0x84000201, 0x0000), /* UART0_TXD */ -_PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0000), /* UART0_RTS# */ -_PAD_CFG_STRUCT(GPP_C11, 0x84000201, 0x0000), /* UART0_CTS# */ -_PAD_CFG_STRUCT(GPP_C12, 0x84000603, 0x0000), /* UART1_RXD */ -_PAD_CFG_STRUCT(GPP_C13, 0x84000700, 0x0000), /* UART1_TXD */ -_PAD_CFG_STRUCT(GPP_C14, 0x84000700, 0x0000), /* UART1_RTS# */ -_PAD_CFG_STRUCT(GPP_C15, 0x84000702, 0x0000), /* UART1_CTS# */ -_PAD_CFG_STRUCT(GPP_C16, 0x84000402, 0x0000), /* I2C0_SDA */ -_PAD_CFG_STRUCT(GPP_C17, 0x84000402, 0x0000), /* I2C0_SCL */ -_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0000), /* I2C1_SDA */ -_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0000), /* I2C1_SCL */ -_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0000), /* UART2_RXD */ -_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0000), /* UART2_TXD */ -_PAD_CFG_STRUCT(GPP_C22, 0x84000201, 0x0000), /* UART2_RTS# */ -_PAD_CFG_STRUCT(GPP_C23, 0x40100102, 0x1000), /* UART2_CTS# */ - -/* ------- GPIO Group GPP_E ------- */ - -_PAD_CFG_STRUCT(GPP_E0, 0x84000300, 0x0000), /* SATAXPCIE0 */ -_PAD_CFG_STRUCT(GPP_E1, 0x84000300, 0x0000), /* SATAXPCIE1 */ -_PAD_CFG_STRUCT(GPP_E2, 0x84000502, 0x3000), /* SATAXPCIE2 */ -_PAD_CFG_STRUCT(GPP_E3, 0x82040102, 0x0000), /* CPU_GP0 */ -_PAD_CFG_STRUCT(GPP_E4, 0x84000201, 0x0000), /* SATA_DEVSLP0 */ -_PAD_CFG_STRUCT(GPP_E5, 0x84000300, 0x0000), /* SATA_DEVSLP1 */ -_PAD_CFG_STRUCT(GPP_E6, 0x84000300, 0x0000), /* SATA_DEVSLP2 */ -_PAD_CFG_STRUCT(GPP_E7, 0x82000102, 0x0000), /* CPU_GP1 */ -_PAD_CFG_STRUCT(GPP_E8, 0x84000700, 0x0000), /* SATALED# */ -_PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000), /* USB2_OC0# */ -_PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000), /* USB2_OC1# */ -_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0000), /* USB2_OC2# */ -_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0000), /* USB2_OC3# */ -_PAD_CFG_STRUCT(GPP_E13, 0x84000700, 0x0000), /* DDPB_HPD0 */ -_PAD_CFG_STRUCT(GPP_E14, 0x84000702, 0x0000), /* DDPC_HPD1 */ -_PAD_CFG_STRUCT(GPP_E15, 0x84000201, 0x0000), /* DDPD_HPD2 */ -_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000), /* GPIO */ -_PAD_CFG_STRUCT(GPP_E17, 0x84000700, 0x0000), /* EDP_HPD */ -_PAD_CFG_STRUCT(GPP_E18, 0x84000702, 0x0000), /* DPPB_CTRLCLK */ -_PAD_CFG_STRUCT(GPP_E19, 0x84000602, 0x0000), /* DPPB_CTRLDATA */ -_PAD_CFG_STRUCT(GPP_E20, 0x84000700, 0x0000), /* DPPC_CTRLCLK */ -_PAD_CFG_STRUCT(GPP_E21, 0x84000602, 0x0000), /* DPPC_CTRLDATA */ -_PAD_CFG_STRUCT(GPP_E22, 0x84000702, 0x0000), /* DPPD_CTRLCLK */ -_PAD_CFG_STRUCT(GPP_E23, 0x84000602, 0x0000), /* DPPD_CTRLDATA */ + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - NC */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + /* GPP_A11 - NC */ + PAD_NC(GPP_A11, UP_20K), + + /* GPP_A12 - NC */ + PAD_NC(GPP_A12, UP_20K), + + /* GPP_A13 - NC */ + PAD_NC(GPP_A13, NONE), + + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + /* GPP_A15 - NC */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - NC */ + PAD_NC(GPP_A16, UP_20K), + + /* GPP_A17 - NC */ + PAD_NC(GPP_A17, UP_20K), + + /* GPP_A18 - NC */ + PAD_NC(GPP_A18, UP_20K), + + /* GPP_A19 - NC */ + PAD_NC(GPP_A19, UP_20K), + + /* GPP_A20 - NC */ + PAD_NC(GPP_A20, UP_20K), + + /* GPP_A21 - NC */ + PAD_NC(GPP_A21, UP_20K), + + /* GPP_A22 - NC */ + PAD_NC(GPP_A22, UP_20K), + + /* GPP_A23 - NC */ + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - Reserved */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - Reserved */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - NC */ + PAD_NC(GPP_B2, UP_20K), + + /* GPP_B3 - NC */ + PAD_NC(GPP_B3, NONE), + + /* GPP_B4 - NC */ + PAD_NC(GPP_B4, UP_20K), + + /* GPP_B5 - NC */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - SRCCLKREQ1# / SSD_CLK_REQ# */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + + /* GPP_B7 - NC */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - SRCCLKREQ3# / LAN2_CLK_REQ# */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + + /* GPP_B9 - NC */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - NC */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - NC */ + PAD_NC(GPP_B11, NONE), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + /* GPP_B15 - NC */ + PAD_NC(GPP_B15, NONE), + + /* GPP_B16 - NC */ + PAD_NC(GPP_B16, NONE), + + /* GPP_B17 - NC */ + PAD_NC(GPP_B17, NONE), + + /* GPP_B18 - NC */ + PAD_NC(GPP_B18, NONE), + + /* GPP_B19 - NC */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - NC */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - NC */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - NC */ + PAD_NC(GPP_B22, UP_20K), + + /* GPP_B23 - NC */ + PAD_NC(GPP_B23, UP_20K), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - NC */ + PAD_NC(GPP_G0, UP_20K), + + /* GPP_G1 - NC */ + PAD_NC(GPP_G1, NONE), + + /* GPP_G2 - NC */ + PAD_NC(GPP_G2, UP_20K), + + /* GPP_G3 - NC */ + PAD_NC(GPP_G3, UP_20K), + + /* GPP_G4 - NC */ + PAD_NC(GPP_G4, UP_20K), + + /* GPP_G5 - NC */ + PAD_NC(GPP_G5, UP_20K), + + /* GPP_G6 - NC */ + PAD_NC(GPP_G6, UP_20K), + + /* GPP_G7 - NC */ + PAD_NC(GPP_G7, DN_20K), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - NC */ + PAD_NC(GPP_D0, UP_20K), + + /* GPP_D1 - NC */ + PAD_NC(GPP_D1, UP_20K), + + /* GPP_D2 - NC */ + PAD_NC(GPP_D2, UP_20K), + + /* GPP_D3 - NC */ + PAD_NC(GPP_D3, UP_20K), + + /* GPP_D4 - NC */ + PAD_NC(GPP_D4, UP_20K), + + /* GPP_D5 - NC */ + PAD_NC(GPP_D5, NONE), + + /* GPP_D6 - NC */ + PAD_NC(GPP_D6, NONE), + + /* GPP_D7 - NC */ + PAD_NC(GPP_D7, UP_20K), + + /* GPP_D8 - NC */ + PAD_NC(GPP_D8, NONE), + + /* GPP_D9 - NC */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - NC */ + PAD_NC(GPP_D11, UP_20K), + + /* GPP_D12 - NC */ + PAD_NC(GPP_D12, UP_20K), + + /* GPP_D13 - NC */ + PAD_NC(GPP_D13, DN_20K), + + /* GPP_D14 - NC */ + PAD_NC(GPP_D14, DN_20K), + + /* GPP_D15 - NC */ + PAD_NC(GPP_D15, UP_20K), + + /* GPP_D16 - NC */ + PAD_NC(GPP_D16, UP_20K), + + /* GPP_D17 - NC */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - NC */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - NC */ + PAD_NC(GPP_D19, NONE), + + /* GPP_D20 - NC */ + PAD_NC(GPP_D20, NONE), + + /* GPP_D21 - NC */ + PAD_NC(GPP_D21, UP_20K), + + /* GPP_D22 - NC */ + PAD_NC(GPP_D22, UP_20K), + + /* GPP_D23 - NC */ + PAD_NC(GPP_D23, UP_20K), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - NC */ + PAD_NC(GPP_F0, UP_20K), + + /* GPP_F1 - NC */ + PAD_NC(GPP_F1, UP_20K), + + /* GPP_F2 - NC */ + PAD_NC(GPP_F2, UP_20K), + + /* GPP_F3 - NC */ + PAD_NC(GPP_F3, UP_20K), + + /* GPP_F4 - NC */ + PAD_NC(GPP_F4, UP_20K), + + /* GPP_F5 - NC */ + PAD_NC(GPP_F5, UP_20K), + + /* GPP_F6 - NC */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - NC */ + PAD_NC(GPP_F7, NONE), + + /* GPP_F8 - NC */ + PAD_NC(GPP_F8, UP_20K), + + /* GPP_F9 - NC */ + PAD_NC(GPP_F9, UP_20K), + + /* GPP_F10 - NC */ + PAD_NC(GPP_F10, UP_20K), + + /* GPP_F11 - NC */ + PAD_NC(GPP_F11, UP_20K), + + /* GPP_F12 - NC */ + PAD_NC(GPP_F12, UP_20K), + + /* GPP_F13 - NC */ + PAD_NC(GPP_F13, UP_20K), + + /* GPP_F14 - NC */ + PAD_NC(GPP_F14, UP_20K), + + /* GPP_F15 - NC */ + PAD_NC(GPP_F15, UP_20K), + + /* GPP_F16 - NC */ + PAD_NC(GPP_F16, UP_20K), + + /* GPP_F17 - NC */ + PAD_NC(GPP_F17, UP_20K), + + /* GPP_F18 - NC */ + PAD_NC(GPP_F18, UP_20K), + + /* GPP_F19 - NC */ + PAD_NC(GPP_F19, UP_20K), + + /* GPP_F20 - NC */ + PAD_NC(GPP_F20, UP_20K), + + /* GPP_F21 - NC */ + PAD_NC(GPP_F21, UP_20K), + + /* GPP_F22 - NC */ + PAD_NC(GPP_F22, UP_20K), + + /* GPP_F23 - NC */ + PAD_NC(GPP_F23, UP_20K), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - NC */ + PAD_NC(GPP_H0, UP_20K), + + /* GPP_H1 - NC# */ + PAD_NC(GPP_H1, NONE), + + /* GPP_H2 - NC */ + PAD_NC(GPP_H2, NONE), + + /* GPP_H3 - NC */ + PAD_NC(GPP_H3, UP_20K), + + /* GPP_H4 - NC */ + PAD_NC(GPP_H4, UP_20K), + + /* GPP_H5 - NC */ + PAD_NC(GPP_H5, UP_20K), + + /* GPP_H6 - NC */ + PAD_NC(GPP_H6, UP_20K), + + /* GPP_H7 - NC */ + PAD_NC(GPP_H7, UP_20K), + + /* GPP_H8 - NC */ + PAD_NC(GPP_H8, UP_20K), + + /* GPP_H9 - NC */ + PAD_NC(GPP_H9, UP_20K), + + /* GPP_H10 - NC */ + PAD_NC(GPP_H10, NONE), + + /* GPP_H11 - NC */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - NC */ + PAD_NC(GPP_H12, UP_20K), + + /* GPP_H13 - NC */ + PAD_NC(GPP_H13, UP_20K), + + /* GPP_H14 - NC */ + PAD_NC(GPP_H14, UP_20K), + + /* GPP_H15 - NC */ + PAD_NC(GPP_H15, UP_20K), + + /* GPP_H16 - NC */ + PAD_NC(GPP_H16, UP_20K), + + /* GPP_H17 - NC */ + PAD_NC(GPP_H17, UP_20K), + + /* GPP_H18 - NC */ + PAD_NC(GPP_H18, UP_20K), + + /* GPP_H19 - NC */ + PAD_NC(GPP_H19, UP_20K), + + /* GPP_H20 - NC */ + PAD_NC(GPP_H20, UP_20K), + + /* GPP_H21 - NC */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - NC */ + PAD_NC(GPP_H22, UP_20K), + + /* GPP_H23 - NC */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), + + /* GPD2 - NC */ + PAD_NC(GPD2, NONE), + + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + + /* GPD6 - NC */ + PAD_NC(GPD6, UP_20K), + + /* GPD7 - NC */ + PAD_NC(GPD7, NONE), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + /* GPD9 - NC */ + PAD_NC(GPD9, UP_20K), + + /* GPD10 - NC */ + PAD_NC(GPD10, UP_20K), + + /* GPD11 - NC */ + PAD_NC(GPD11, UP_20K), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - NC */ + PAD_NC(GPP_C2, NONE), + + /* GPP_C3 - NC */ + PAD_NC(GPP_C3, NONE), + + /* GPP_C4 - NC */ + PAD_NC(GPP_C4, NONE), + + /* GPP_C5 - NC */ + PAD_NC(GPP_C5, UP_20K), + + /* GPP_C6 - NC */ + PAD_NC(GPP_C6, NONE), + + /* GPP_C7 - NC */ + PAD_NC(GPP_C7, NONE), + + /* GPP_C8 - NC */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - NC */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - NC */ + PAD_NC(GPP_C10, UP_20K), + + /* GPP_C11 - NC */ + PAD_NC(GPP_C11, UP_20K), + + /* GPP_C12 - NC */ + PAD_NC(GPP_C12, UP_20K), + + /* GPP_C13 - NC */ + PAD_NC(GPP_C13, UP_20K), + + /* GPP_C14 - NC */ + PAD_NC(GPP_C14, UP_20K), + + /* GPP_C15 - NC */ + PAD_NC(GPP_C15, UP_20K), + + /* GPP_C16 - NC */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - NC */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - NC */ + PAD_NC(GPP_C18, UP_20K), + + /* GPP_C19 - NC */ + PAD_NC(GPP_C19, UP_20K), + + /* GPP_C20 - NC */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - NC */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - USB3_P1_PWREN */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - NC */ + PAD_NC(GPP_C23, UP_20K), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - NC */ + PAD_NC(GPP_E0, UP_20K), + + /* GPP_E1 - NC */ + PAD_NC(GPP_E1, UP_20K), + + /* GPP_E2 - SATAXPCIE2 */ + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + + /* GPP_E3 - NC */ + PAD_NC(GPP_E3, UP_20K), + + /* GPP_E4 - SATA_DEVSLP0 */ + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), + + /* GPP_E5 - NC */ + PAD_NC(GPP_E5, UP_20K), + + /* GPP_E6 - NC */ + PAD_NC(GPP_E6, UP_20K), + + /* GPP_E7 - NC */ + PAD_NC(GPP_E7, NONE), + + /* GPP_E8 - SATALED# */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* GPP_E9 - USB2_OC0# */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + /* GPP_E10 - USB2_OC1# */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* GPP_E11 - USB2_OC2# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + + /* GPP_E12 - USB2_OC3# */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPP_E13 - DDPB_HPD0 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* GPP_E14 - DDPC_HPD1 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - NC */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), + + /* GPP_E17 - NC */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - DPPB_CTRLCLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* GPP_E19 - DPPB_CTRLDATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + + /* GPP_E20 - NC */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - NC */ + PAD_NC(GPP_E21, NONE), + + /* GPP_E22 - NC */ + PAD_NC(GPP_E22, UP_20K), + + /* GPP_E23 - NC */ + PAD_NC(GPP_E23, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) -- 2.20.1