From f75ddb81c32957c0d0f6dfd9a72361e6914d4f59 Mon Sep 17 00:00:00 2001 From: gaspar-ilom Date: Tue, 14 Jan 2025 13:20:05 +0100 Subject: [PATCH] add t480 board Signed-off-by: gaspar-ilom --- .circleci/config.yml | 15 + BOARD_TESTERS.md | 5 + blobs/kabylake/.gitignore | 3 + blobs/kabylake/fetch_split_fsp.sh | 59 + blobs/xx80/.gitignore | 1 + blobs/xx80/README | 30 + blobs/xx80/download_clean_deguard_me.sh | 131 + blobs/xx80/gbe.bin | Bin 0 -> 8192 bytes blobs/xx80/hashes.txt | 5 + blobs/xx80/ifd.bin | Bin 0 -> 4096 bytes .../t480-hotp-maximized.config | 70 + boards/t480-maximized/t480-maximized.config | 69 + config/coreboot-t480-maximized.config | 907 +++++++ config/coreboot-t480.config | 868 +++++++ ...zalia_device.h-Correct-location2-shi.patch | 49 + ...erge-enums-from-azalia_device.h-and-.patch | 552 ++++ ...zalia_device.h-Merge-location1-and-l.patch | 194 ++ ...parate-codec-checking-and-initializa.patch | 173 ++ .../0009-azalia-Get-rid-of-return-1-0.patch | 301 +++ ...e-Enable-4E-4F-PNP-I-O-ports-in-boot.patch | 30 + ...Add-ThinkPad-T480-and-ThinkPad-T480s.patch | 2237 +++++++++++++++++ targets/xx80_me_blobs.mk | 27 + 22 files changed, 5726 insertions(+) create mode 100644 blobs/kabylake/.gitignore create mode 100755 blobs/kabylake/fetch_split_fsp.sh create mode 100644 blobs/xx80/.gitignore create mode 100644 blobs/xx80/README create mode 100755 blobs/xx80/download_clean_deguard_me.sh create mode 100644 blobs/xx80/gbe.bin create mode 100644 blobs/xx80/hashes.txt create mode 100644 blobs/xx80/ifd.bin create mode 100644 boards/t480-hotp-maximized/t480-hotp-maximized.config create mode 100644 boards/t480-maximized/t480-maximized.config create mode 100644 config/coreboot-t480-maximized.config create mode 100644 config/coreboot-t480.config create mode 100644 patches/coreboot-24.02.01/0005-include-device-azalia_device.h-Correct-location2-shi.patch create mode 100644 patches/coreboot-24.02.01/0006-include-device-Merge-enums-from-azalia_device.h-and-.patch create mode 100644 patches/coreboot-24.02.01/0007-include-device-azalia_device.h-Merge-location1-and-l.patch create mode 100644 patches/coreboot-24.02.01/0008-device-azalia-Separate-codec-checking-and-initializa.patch create mode 100644 patches/coreboot-24.02.01/0009-azalia-Get-rid-of-return-1-0.patch create mode 100644 patches/coreboot-24.02.01/0010-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch create mode 100644 patches/coreboot-24.02.01/0011-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch create mode 100644 targets/xx80_me_blobs.mk diff --git a/.circleci/config.yml b/.circleci/config.yml index 6ff83e20..026719f8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -424,6 +424,20 @@ workflows: requires: - x230-hotp-maximized + - build: + name: t480-maximized + target: t480-maximized + subcommand: "" + requires: + - x230-hotp-maximized + + - build: + name: t480-hotp-maximized + target: t480-hotp-maximized + subcommand: "" + requires: + - x230-hotp-maximized + - build: name: UNTESTED_w541-maximized target: UNTESTED_w541-maximized @@ -556,3 +570,4 @@ workflows: subcommand: "" requires: - librem_l1um + diff --git a/BOARD_TESTERS.md b/BOARD_TESTERS.md index 622fc3de..e34c3b63 100644 --- a/BOARD_TESTERS.md +++ b/BOARD_TESTERS.md @@ -32,6 +32,11 @@ xx4x(Haswell): - [ ] t440p: @fhvyhjriur @ThePlexus @srgrint @akunterkontrolle @rbreslow - [ ] w541 (similar to t440p): @ResendeGHF @gaspar-ilom (Always tested late: Needs more responsive board testers or risk to become unmaintained.) +xx8x(Kaby Lake Refresh): +=== +- [ ] t480: @gaspar-ilom +- [ ] t480s (similar to t480): TODO: NOT SUPPORTED OR TESTED YET + Librems: === - [ ] Librem 11(JasperLake): @JonathonHall-Purism diff --git a/blobs/kabylake/.gitignore b/blobs/kabylake/.gitignore new file mode 100644 index 00000000..143d29a2 --- /dev/null +++ b/blobs/kabylake/.gitignore @@ -0,0 +1,3 @@ +Fsp_M.fd +Fsp_S.fd +Fsp_T.fd \ No newline at end of file diff --git a/blobs/kabylake/fetch_split_fsp.sh b/blobs/kabylake/fetch_split_fsp.sh new file mode 100755 index 00000000..4cd362e9 --- /dev/null +++ b/blobs/kabylake/fetch_split_fsp.sh @@ -0,0 +1,59 @@ +#!/usr/bin/env bash + +function usage() { + echo -n \ + "Usage: $(basename "$0") path_to_output_directory +Get FSP from coreboot git submodule and split. +" +} + +# Integrity checks for the coreboot provided fsp blob... +FSP_FD_COREBOOT_HASH="ddfbc51430699e0dfcb24a60bcb5b6e5481b325ebecf1ac177e069013189e4b0" +FSP_SUBMODULE_PATH="3rdparty/fsp" +PATH_TO_FSP_FD_IN_SUBMODULE="KabylakeFspBinPkg/Fsp.fd" +SPLIT_FSP_PATH_IN_SUBMODULE="Tools/SplitFspBin.py" + + +split_fsp() +{ + fsp_binary="$1" + fsp_output_dir="$2" + split_fsp_py="${COREBOOT_DIR}/${FSP_SUBMODULE_PATH}/${SPLIT_FSP_PATH_IN_SUBMODULE}" + python "$split_fsp_py" split -f "$fsp_binary" -o "$fsp_output_dir" -n "Fsp.fd" || exit 1 +} + +if [[ "${BASH_SOURCE[0]}" == "$0" ]]; then + if [[ "${1:-}" == "--help" ]]; then + usage + else + output_dir="$(realpath "${1:-./}")" + fsp_m_path="${output_dir}/Fsp_M.fd" + fsp_s_path="${output_dir}/Fsp_S.fd" + #chk_exists + + if [[ -z "${COREBOOT_DIR}" ]]; then + echo "ERROR: No COREBOOT_DIR variable defined." + exit 1 + fi + + # TODO chk_exists above + # if [[ ! -f "$fsp_s_path" ]] || [[ ! -f "$fsp_m_path" ]] || [ "$retry" = "y" ]; then + git -C "$COREBOOT_DIR" submodule update --init --checkout "$FSP_SUBMODULE_PATH" + fsp_fd="${COREBOOT_DIR}/${FSP_SUBMODULE_PATH}/${PATH_TO_FSP_FD_IN_SUBMODULE}" + chk_sha256sum "$FSP_FD_COREBOOT_HASH" "$fsp_fd" + pushd "$(mktemp -d)" || exit + fsp_file="Fsp.fd" + cp "$fsp_fd" "$fsp_file" + + split_fsp "$(pwd)/${fsp_file}" "$output_dir" + + rm -rf ./* + popd || exit + git -C "$COREBOOT_DIR" submodule deinit "$FSP_SUBMODULE_PATH" + # fi + + # TODO final checksums + # chk_sha256sum "$FSP_FD_COREBOOT_HASH" "$fsp_s_path" + # chk_sha256sum "$FSP_FD_COREBOOT_HASH" "$fsp_m_path" + fi +fi \ No newline at end of file diff --git a/blobs/xx80/.gitignore b/blobs/xx80/.gitignore new file mode 100644 index 00000000..24d49395 --- /dev/null +++ b/blobs/xx80/.gitignore @@ -0,0 +1 @@ +me.bin diff --git a/blobs/xx80/README b/blobs/xx80/README new file mode 100644 index 00000000..082926c1 --- /dev/null +++ b/blobs/xx80/README @@ -0,0 +1,30 @@ +The ME blobs dumped in this directory come from the following link: https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe + +This provides ME version 11.6.0.1126. In this version CVE-2017-5705 has not yet been fixed. +See https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html +Therefore, Bootguard can be disabled by deguard with a patched ME. + +1.0.0:Automatically extract, neuter and deguard me.bin +download_clean_me.sh : Downloads vulnerable ME from Dell verify checksum, extract ME, neuters ME, relocate and trim it, then apply deguard patch and place it into me.bin + +sha256sum: +1990b42df67ba70292f4f6e2660efb909917452dcb9bd4b65ea2f86402cfa16b me.bin + +1.0.1: Extract blobs from original rom: +extract.sh: takes backup, unlocks ifd, apply me_cleaner to neuter, relocate, trim and deguard it, modify BIOS and ME region of IFD and place output files into this dir. + +sha256sum: will vary depending of IFD and ME extracted where IFD regions of BIOS and ME should be consistent. + +1.1: More blobs +-------------------- +ifd.bin was extracted from a T480 from an external flashrom backup. + +sha256sum: +f2f6d5fb0a5e02964b494862032fd93f1f88e2febd9904b936083600645c7fdf ifd.bin + +sha256sum: +6b7f3912995fb87ae62956e009470b35b72b5b9a4bfd7bed48da429af9804866 gbe.bin +------------------------ + +Notes: as specified in first link, this ME can be deployed to: + T480 and T480s \ No newline at end of file diff --git a/blobs/xx80/download_clean_deguard_me.sh b/blobs/xx80/download_clean_deguard_me.sh new file mode 100755 index 00000000..6bed9043 --- /dev/null +++ b/blobs/xx80/download_clean_deguard_me.sh @@ -0,0 +1,131 @@ +#!/usr/bin/env bash + +# These variables are all for the deguard tool. +# They would need to be changed if using the tool for other devices like the T480s or with a different ME version... +ME_delta="thinkpad_t480" +ME_version="11.6.0.1126" +ME_sku="2M" +ME_pch="LP" + +# Integrity checks for the vendor provided ME blob... +ME_DOWNLOAD_HASH="ddfbc51430699e0dfcb24a60bcb5b6e5481b325ebecf1ac177e069013189e4b0" +# ...and the cleaned and deguarded version from that blob. +DEGUARDED_ME_BIN_HASH="1990b42df67ba70292f4f6e2660efb909917452dcb9bd4b65ea2f86402cfa16b" + +function usage() { + echo -n \ + "Usage: $(basename "$0") path_to_output_directory +Download Intel ME firmware from Dell, neutralize and shrink keeping the MFS. +" +} + +function chk_sha256sum() { + sha256_hash="$1"; filename="$2" + echo "$sha256_hash" "$filename" "$(pwd)" + sha256sum "$filename" + if ! echo "${sha256_hash} ${filename}" | sha256sum --check; then + echo "ERROR: SHA256 checksum for ${filename} doesn't match." + exit 1 + fi +} + +function chk_exists() { + if [ -e "$me_deguarded" ]; then + echo "me.bin already exists" + if echo "${DEGUARDED_ME_BIN_HASH} $me_deguarded" | sha256sum --check; then + echo "SKIPPING: SHA256 checksum for me.bin matches." + exit 0 + fi + retry="y" + echo "me.bin exists but checksum doesn't match. Continuing..." + fi +} + +function download_and_clean() { + me_output="$(realpath "${1}")" + + # Download and unpack the Dell installer into a temporary directory and + # extract the deguardable Intel ME blob. + pushd "$(mktemp -d)" || exit + + # Download the installer that contains the ME blob + me_installer_filename="Inspiron_5468_1.3.0.exe" + user_agent="Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Firefox/91.0" + curl -A "$user_agent" -s -O "https://dl.dell.com/FOLDER04573471M/1/${me_installer_filename}" + chk_sha256sum "$ME_DOWNLOAD_HASH" "$me_installer_filename" + + # Download the tool to unpack Dell's installer and unpack the ME blob. + git clone https://github.com/platomav/BIOSUtilities + git -C BIOSUtilities checkout ef50b75ae115ae8162fa8b0a7b8c42b1d2db894b + + python "BIOSUtilities/Dell_PFS_Extract.py" "${me_installer_filename}" -e || exit + + extracted_me_filename="1 Inspiron_5468_1.3.0 -- 3 Intel Management Engine (Non-VPro) Update v${ME_version}.bin" + + mv "${me_installer_filename}_extracted/Firmware/${extracted_me_filename}" "${COREBOOT_DIR}/util/me_cleaner" + rm -rf ./* + popd || exit + + # Neutralize and shrink Intel ME. Note that this doesn't include + # --soft-disable to set the "ME Disable" or "ME Disable B" (e.g., + # High Assurance Program) bits, as they are defined within the Flash + # Descriptor. + # However, the HAP bit must be enabled to make the deguarded ME work. We only clean the ME in this function. + # https://github.com/corna/me_cleaner/wiki/External-flashing#neutralize-and-shrink-intel-me-useful-only-for-coreboot + pushd "${COREBOOT_DIR}/util/me_cleaner" || exit + + # MFS is needed for deguard so we whitelist it here and also do not relocate the FTPR partition + python me_cleaner.py --whitelist MFS -t -O "$me_output" "$extracted_me_filename" + rm -f "$extracted_me_filename" + popd || exit +} + +function deguard() { + me_input="$(realpath "${1}")" + me_output="$(realpath "${2}")" + + # Download the deguard tool into a temporary directory and apply the patch to the cleaned ME blob. + pushd "$(mktemp -d)" || exit + git clone https://review.coreboot.org/deguard.git + pushd deguard || exit + git checkout 0ed3e4ff824fc42f71ee22907d0594ded38ba7b2 + + python ./finalimage.py \ + --delta "data/delta/$ME_delta" \ + --version "$ME_version" \ + --pch "$ME_pch" \ + --sku "$ME_sku" \ + --fake-fpfs data/fpfs/zero \ + --input "$me_input" \ + --output "$me_output" + + popd || exit + #Cleanup + rm -rf ./* + popd || exit +} + +if [[ "${BASH_SOURCE[0]}" == "$0" ]]; then + if [[ "${1:-}" == "--help" ]]; then + usage + else + + output_dir="$(realpath "${1:-./}")" + me_cleaned="${output_dir}/me_cleaned.bin" + me_deguarded="${output_dir}/me.bin" + chk_exists + + if [[ -z "${COREBOOT_DIR}" ]]; then + echo "ERROR: No COREBOOT_DIR variable defined." + exit 1 + fi + + if [[ ! -f "$me_deguarded" ]] || [ "$retry" = "y" ]; then + download_and_clean "$me_cleaned" + deguard "$me_cleaned" "$me_deguarded" + rm -f "$me_cleaned" + fi + + chk_sha256sum "$DEGUARDED_ME_BIN_HASH" "$me_deguarded" + fi +fi diff --git a/blobs/xx80/gbe.bin b/blobs/xx80/gbe.bin new file mode 100644 index 0000000000000000000000000000000000000000..dfb2300d7734e85cb289ae431b3237604a0ce73d GIT binary patch literal 8192 zcmb2DX|I0V&B*cpzX-#528IR(f&c#x3&bj|62C6W00RxI%XJJG1b|$gBrPT`XAWV; z>!NFST^GFpCP6Hq)&>T@HV%*$b_NCo1rUP|h#46iG=$h4{$l_JrvLw~LqW{~9pp%rRu}*=E4N3gjb99%YS&z-S0$2DdOXVrIZm5ws9swnY;Fa`*6Hij9hl zh5)G{Fj@+YhQMeDjE2By2#kinXb6m~5b!fH334?s4)^i(ar6T=9O&(PsnPyFy@Pzz zzR?gEG$AnB|0k}uHroFuE}TYHksbnrrZ5`~LtM CN`F28 literal 0 HcmV?d00001 diff --git a/blobs/xx80/hashes.txt b/blobs/xx80/hashes.txt new file mode 100644 index 00000000..bc3da7b1 --- /dev/null +++ b/blobs/xx80/hashes.txt @@ -0,0 +1,5 @@ +8e48eb06740a0c250eea0d17a8610106cbd76a50e3bee3485642fd46a8204f02 Fsp_M.fd +c2f4ee42ba15b315ad3b282375af9151ce3f9e7d81ea3537ffc404e7e20f1f9a Fsp_S.fd +6b7f3912995fb87ae62956e009470b35b72b5b9a4bfd7bed48da429af9804866 gbe.bin +f2f6d5fb0a5e02964b494862032fd93f1f88e2febd9904b936083600645c7fdf ifd.bin +1990b42df67ba70292f4f6e2660efb909917452dcb9bd4b65ea2f86402cfa16b me.bin \ No newline at end of file diff --git a/blobs/xx80/ifd.bin b/blobs/xx80/ifd.bin new file mode 100644 index 0000000000000000000000000000000000000000..cdeaee4a484065cb6ab65e22c9d28d63117a1ddc GIT binary patch literal 4096 zcmeH~u}T9$5QhJ~&0!M6oW#Hhf-9KDDk|27z>&sA@EWmD@Bz|TSS6Lcl}})4En14; zWB3S35wST~|G7JYM>J)SxO4n7+|2IG?swH$TeQ>rQB9+SvKMq(dKbm2wI4X!+v=P@ zJU+d?Ne#3$Wx1!W6g=2Iev$3}^vHmTq*>lmde6gvV?fE^@5aPbPBV9RR4inRdQ55$ zxXfELc0dw9nKD$HI-meQ^(*wU^P~ajJST-KmTyN@`cwj6{u-Y-pk=XtRI3o}5b-e47h z&~fGnI0BA +Date: Fri, 23 Feb 2024 10:28:08 +0900 +Subject: [PATCH 05/11] include/device/azalia_device.h: Correct location2 shift + to 28 bits +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The location is specified to be in range of 29:24, which is further +divided into upper bits (location2) [5:4] and lower bits (location1) +[3:0]. + +This also corrects the resulting values of clevo/l140mu. + +References: + - Intel High Definition Audio Specification, rev. 1.0a, page 178, + Figure 74. Configuration Data Structure. + +TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the +same binary. + +Change-Id: Ia5a3431b70783cb88e866d0fd8ea5530100f3d52 +Signed-off-by: Nicholas Sudsgaard +Reviewed-on: https://review.coreboot.org/c/coreboot/+/80727 +Reviewed-by: Felix Singer +Reviewed-by: Michael Niewöhner +Reviewed-by: Nico Huber +Tested-by: build bot (Jenkins) +--- + src/include/device/azalia_device.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h +index f7c1448863..42807fdd46 100644 +--- a/src/include/device/azalia_device.h ++++ b/src/include/device/azalia_device.h +@@ -120,7 +120,7 @@ enum azalia_pin_misc { + #define AZALIA_PIN_DESC(conn, location2, location1, dev, type, color, misc, \ + association, sequence) \ + (((conn) << 30) | \ +- ((location2) << 27) | \ ++ ((location2) << 28) | \ + ((location1) << 24) | \ + ((dev) << 20) | \ + ((type) << 16) | \ +-- +2.39.5 + diff --git a/patches/coreboot-24.02.01/0006-include-device-Merge-enums-from-azalia_device.h-and-.patch b/patches/coreboot-24.02.01/0006-include-device-Merge-enums-from-azalia_device.h-and-.patch new file mode 100644 index 00000000..4241a8e0 --- /dev/null +++ b/patches/coreboot-24.02.01/0006-include-device-Merge-enums-from-azalia_device.h-and-.patch @@ -0,0 +1,552 @@ +From 3ef328a60902ae7fdf14786c3088522feb4df044 Mon Sep 17 00:00:00 2001 +From: Nicholas Sudsgaard +Date: Thu, 22 Feb 2024 13:33:15 +0900 +Subject: [PATCH 06/11] include/device: Merge enums from azalia_device.h and + azalia.h +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We were keeping 2 copies of the same thing (albeit there were some +slight differences). As azalia_device.h is used much more in the +codebase this was kept as the base and then some of the nice features +of azalia.h were incorporated. + +The significant changes are: + - All enum names now use the `AZALIA_` prefix. + +This also drops the AzaliaPinConfiguration enum as it was never used +since added in 2013. + +Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e +Signed-off-by: Nicholas Sudsgaard +Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695 +Reviewed-by: Nico Huber +Tested-by: build bot (Jenkins) +Reviewed-by: Felix Singer +Reviewed-by: Michael Niewöhner +--- + src/include/device/azalia.h | 115 ------------- + src/include/device/azalia_device.h | 158 +++++++++--------- + .../clevo/tgl-u/variants/l140mu/hda_verb.c | 70 ++++---- + .../siemens/chili/variants/chili/hda_verb.c | 73 ++++---- + 4 files changed, 157 insertions(+), 259 deletions(-) + delete mode 100644 src/include/device/azalia.h + +diff --git a/src/include/device/azalia.h b/src/include/device/azalia.h +deleted file mode 100644 +index 24f91d9755..0000000000 +--- a/src/include/device/azalia.h ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0-only */ +-#ifndef AZALIA_H_ +-#define AZALIA_H_ +- +-/* +- * The tables found in this file are derived from the Intel High Definition +- * Audio Specification Revision 1.0a, published 17 June 2010 +- */ +- +-/* +- * Page 177: Default Pin Configuration +- */ +- +-enum AzaliaPinCfgPortConnectivity { +- AZALIA_PINCFG_PORT_JACK = 0, +- AZALIA_PINCFG_PORT_NC = 1, +- AZALIA_PINCFG_PORT_FIXED = 2, +- AZALIA_PINCFG_PORT_MULTIPLE = 3, +-}; +- +-enum AzaliaPinCfgLocationGross { +- AZALIA_PINCFG_LOCATION_EXTERNAL = 0x00, +- AZALIA_PINCFG_LOCATION_INTERNAL = 0x10, +- AZALIA_PINCFG_LOCATION_EXT_CHASSIS = 0x20, +- AZALIA_PINCFG_LOCATION_OTHER = 0x30, +-}; +- +-enum AzaliaPinCfgLocationFine { +- AZALIA_PINCFG_LOCATION_NOT_APPLICABLE = 0x00, +- AZALIA_PINCFG_LOCATION_REAR = 0x01, +- AZALIA_PINCFG_LOCATION_FRONT = 0x02, +- AZALIA_PINCFG_LOCATION_LEFT = 0x03, +- AZALIA_PINCFG_LOCATION_RIGHT = 0x04, +- AZALIA_PINCFG_LOCATION_TOP = 0x05, +- AZALIA_PINCFG_LOCATION_BOTTOM = 0x06, +-}; +- +-enum AzaliaPinCfgLocationSpecial { +- AZALIA_PINCFG_LOCATION_REAR_PANEL = 0x07, +- AZALIA_PINCFG_LOCATION_DRIVE_BAY = 0x08, +- AZALIA_PINCFG_LOCATION_RISER_CARD = 0x17, +- AZALIA_PINCFG_LOCATION_DIGITAL_DISPLAY = 0x18, +- AZALIA_PINCFG_LOCATION_ATAPI = 0x19, +- AZALIA_PINCFG_LOCATION_INSIDE_LID = 0x37, +- AZALIA_PINCFG_LOCATION_OUTSIDE_LID = 0x38, +-}; +- +-enum AzaliaPinCfgDefaultDevice { +- AZALIA_PINCFG_DEVICE_LINEOUT = 0x0, +- AZALIA_PINCFG_DEVICE_SPEAKER = 0x1, +- AZALIA_PINCFG_DEVICE_HP_OUT = 0x2, +- AZALIA_PINCFG_DEVICE_CD = 0x3, +- AZALIA_PINCFG_DEVICE_SPDIF_OUT = 0x4, +- AZALIA_PINCFG_DEVICE_DIGITAL_OUT = 0x5, +- AZALIA_PINCFG_DEVICE_MODEM_LINE = 0x6, +- AZALIA_PINCFG_DEVICE_MODEM_HANDSET = 0x7, +- AZALIA_PINCFG_DEVICE_LINEIN = 0x8, +- AZALIA_PINCFG_DEVICE_AUX = 0x9, +- AZALIA_PINCFG_DEVICE_MICROPHONE = 0xA, +- AZALIA_PINCFG_DEVICE_TELEPHONY = 0xB, +- AZALIA_PINCFG_DEVICE_SPDIF_IN = 0xC, +- AZALIA_PINCFG_DEVICE_DIGITAL_IN = 0xD, +- AZALIA_PINCFG_DEVICE_OTHER = 0xF, +-}; +- +-enum AzaliaPinCfgConnectionType { +- AZALIA_PINCFG_CONN_UNKNOWN = 0x0, +- AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK = 0x1, +- AZALIA_PINCFG_CONN_STEREO_PHONE_JACK = 0x2, +- AZALIA_PINCFG_CONN_INTERNAL_ATAPI = 0x3, +- AZALIA_PINCFG_CONN_RCA = 0x4, +- AZALIA_PINCFG_CONN_OPTICAL = 0x5, +- AZALIA_PINCFG_CONN_OTHER_DIGITAL = 0x6, +- AZALIA_PINCFG_CONN_OTHER_ANALOG = 0x7, +- AZALIA_PINCFG_CONN_DIN_PLUG = 0x8, +- AZALIA_PINCFG_CONN_XLR = 0x9, +- AZALIA_PINCFG_CONN_MODEM_RJ11 = 0xA, +- AZALIA_PINCFG_CONN_COMBINATION = 0xB, +- AZALIA_PINCFG_CONN_OTHER = 0xF, +-}; +- +-enum AzaliaPinCfgColor { +- AZALIA_PINCFG_COLOR_UNKNOWN = 0x0, +- AZALIA_PINCFG_COLOR_BLACK = 0x1, +- AZALIA_PINCFG_COLOR_GREY = 0x2, +- AZALIA_PINCFG_COLOR_BLUE = 0x3, +- AZALIA_PINCFG_COLOR_GREEN = 0x4, +- AZALIA_PINCFG_COLOR_RED = 0x5, +- AZALIA_PINCFG_COLOR_ORANGE = 0x6, +- AZALIA_PINCFG_COLOR_YELLOW = 0x7, +- AZALIA_PINCFG_COLOR_PURPLE = 0x8, +- AZALIA_PINCFG_COLOR_PINK = 0x9, +- AZALIA_PINCFG_COLOR_WHITE = 0xE, +- AZALIA_PINCFG_COLOR_OTHER = 0xF, +-}; +- +-enum AzaliaPinCfgMisc { +- AZALIA_PINCFG_MISC_IGNORE_PRESENCE = 0x1, +-}; +- +-union AzaliaPinConfiguration { +- unsigned int value; +- struct __attribute__((aligned(4), packed)) { +- enum AzaliaPinCfgPortConnectivity port:2; +- unsigned char location:6; +- enum AzaliaPinCfgDefaultDevice device:4; +- enum AzaliaPinCfgConnectionType connection:4; +- enum AzaliaPinCfgColor color:4; +- unsigned char misc:4; +- unsigned char association:4; +- unsigned char sequence:4; +- }; +-}; +- +-#endif /* AZALIA_H_ */ +diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h +index 42807fdd46..4d9298cf95 100644 +--- a/src/include/device/azalia_device.h ++++ b/src/include/device/azalia_device.h +@@ -4,8 +4,8 @@ + #define DEVICE_AZALIA_H + + #include +-#include + #include ++#include + #include + + #define HDA_GCAP_REG 0x00 +@@ -36,98 +36,104 @@ extern const u32 cim_verb_data_size; + extern const u32 pc_beep_verbs[]; + extern const u32 pc_beep_verbs_size; + ++/* ++ * The tables found in this file are derived from the Intel High Definition ++ * Audio Specification Revision 1.0a, published 17 June 2010 ++ * ++ * 7.3.3.31 Configuration Default (page 177) ++ */ + enum azalia_pin_connection { +- JACK = 0, +- NC, +- INTEGRATED, +- JACK_AND_INTEGRATED, ++ AZALIA_JACK = 0x0, ++ AZALIA_NC = 0x1, ++ AZALIA_INTEGRATED = 0x2, ++ AZALIA_JACK_AND_INTEGRATED = 0x3, + }; + +-enum azalia_pin_color { +- COLOR_UNKNOWN = 0, +- BLACK, +- GREY, +- BLUE, +- GREEN, +- RED, +- ORANGE, +- YELLOW, +- PURPLE, +- PINK, +- WHITE = 0xe, +- COLOR_OTHER = 0xf, ++enum azalia_pin_location_gross { ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS = 0x0, ++ AZALIA_INTERNAL = 0x1, ++ AZALIA_SEPARATE_CHASSIS = 0x2, ++ AZALIA_LOCATION_OTHER = 0x3, + }; + +-enum azalia_pin_type { +- TYPE_UNKNOWN = 0, +- STEREO_MONO_1_8, +- STEREO_MONO_1_4, +- ATAPI, +- RCA, +- OPTICAL, +- OTHER_DIGITAL, +- OTHER_ANALOG, +- MULTICHANNEL_ANALOG, +- XLR, +- RJ_11, +- COMBINATION, +- TYPE_OTHER = 0xf ++enum azalia_pin_location_geometric { ++ AZALIA_GEOLOCATION_NA = 0x0, ++ AZALIA_REAR = 0x1, ++ AZALIA_FRONT = 0x2, ++ AZALIA_LEFT = 0x3, ++ AZALIA_RIGHT = 0x4, ++ AZALIA_TOP = 0x5, ++ AZALIA_BOTTOM = 0x6, ++ AZALIA_SPECIAL7 = 0x7, ++ AZALIA_SPECIAL8 = 0x8, ++ AZALIA_SPECIAL9 = 0x9, + }; + + enum azalia_pin_device { +- LINE_OUT = 0, +- SPEAKER, +- HP_OUT, +- CD, +- SPDIF_OUT, +- DIGITAL_OTHER_OUT, +- MODEM_LINE_SIDE, +- MODEM_HANDSET_SIDE, +- LINE_IN, +- AUX, +- MIC_IN, +- TELEPHONY, +- SPDIF_IN, +- DIGITAL_OTHER_IN, +- DEVICE_OTHER = 0xf, ++ AZALIA_LINE_OUT = 0x0, ++ AZALIA_SPEAKER = 0x1, ++ AZALIA_HP_OUT = 0x2, ++ AZALIA_CD = 0x3, ++ AZALIA_SPDIF_OUT = 0x4, ++ AZALIA_DIGITAL_OTHER_OUT = 0x5, ++ AZALIA_MODEM_LINE_SIDE = 0x6, ++ AZALIA_MODEM_HANDSET_SIDE = 0x7, ++ AZALIA_LINE_IN = 0x8, ++ AZALIA_AUX = 0x9, ++ AZALIA_MIC_IN = 0xa, ++ AZALIA_TELEPHONY = 0xb, ++ AZALIA_SPDIF_IN = 0xc, ++ AZALIA_DIGITAL_OTHER_IN = 0xd, ++ AZALIA_DEVICE_OTHER = 0xf, + }; + +-enum azalia_pin_location_1 { +- NA = 0, +- REAR, +- FRONT, +- LEFT, +- RIGHT, +- TOP, +- BOTTOM, +- SPECIAL7, +- SPECIAL8, +- SPECIAL9, ++enum azalia_pin_type { ++ AZALIA_TYPE_UNKNOWN = 0x0, ++ AZALIA_STEREO_MONO_1_8 = 0x1, ++ AZALIA_STEREO_MONO_1_4 = 0x2, ++ AZALIA_ATAPI_INTERNAL = 0x3, ++ AZALIA_RCA = 0x4, ++ AZALIA_OPTICAL = 0x5, ++ AZALIA_OTHER_DIGITAL = 0x6, ++ AZALIA_OTHER_ANALOG = 0x7, ++ AZALIA_MULTICHANNEL_ANALOG = 0x8, ++ AZALIA_XLR = 0x9, ++ AZALIA_RJ_11 = 0xa, ++ AZALIA_COMBINATION = 0xb, ++ AZALIA_TYPE_OTHER = 0xf, + }; + +-enum azalia_pin_location_2 { +- EXTERNAL_PRIMARY_CHASSIS = 0, +- INTERNAL, +- SEPARATE_CHASSIS, +- LOCATION_OTHER ++enum azalia_pin_color { ++ AZALIA_COLOR_UNKNOWN = 0x0, ++ AZALIA_BLACK = 0x1, ++ AZALIA_GREY = 0x2, ++ AZALIA_BLUE = 0x3, ++ AZALIA_GREEN = 0x4, ++ AZALIA_RED = 0x5, ++ AZALIA_ORANGE = 0x6, ++ AZALIA_YELLOW = 0x7, ++ AZALIA_PURPLE = 0x8, ++ AZALIA_PINK = 0x9, ++ AZALIA_WHITE = 0xe, ++ AZALIA_COLOR_OTHER = 0xf, + }; + + enum azalia_pin_misc { +- JACK_PRESENCE_DETECT = 0, +- NO_JACK_PRESENCE_DETECT, ++ AZALIA_JACK_PRESENCE_DETECT = 0x0, ++ AZALIA_NO_JACK_PRESENCE_DETECT = 0x1, + }; + +-#define AZALIA_PIN_DESC(conn, location2, location1, dev, type, color, misc, \ +- association, sequence) \ +- (((conn) << 30) | \ +- ((location2) << 28) | \ +- ((location1) << 24) | \ +- ((dev) << 20) | \ +- ((type) << 16) | \ +- ((color) << 12) | \ +- ((misc) << 8) | \ +- ((association) << 4) | \ +- ((sequence) << 0)) ++#define AZALIA_PIN_DESC(conn, location2, location1, dev, type, color, misc, \ ++ association, sequence) \ ++ ((((conn) << 30) & 0xc0000000) | \ ++ (((location2) << 28) & 0x30000000) | \ ++ (((location1) << 24) & 0x0f000000) | \ ++ (((dev) << 20) & 0x00f00000) | \ ++ (((type) << 16) & 0x000f0000) | \ ++ (((color) << 12) & 0x0000f000) | \ ++ (((misc) << 8) & 0x00000f00) | \ ++ (((association) << 4) & 0x000000f0) | \ ++ (((sequence) << 0) & 0x0000000f)) + + #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ + ARRAY_SIZE(pc_beep_verbs); \ +diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +index 0ff24a2c79..2e1a5799d7 100644 +--- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c ++++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +@@ -12,61 +12,61 @@ const u32 cim_verb_data[] = { + + /* Microphone (display lid), vendor value: 0x90a60130 */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( +- INTEGRATED, +- LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */ +- SPECIAL7, /* lid, vendor: NA */ +- MIC_IN, +- OTHER_DIGITAL, +- COLOR_UNKNOWN, +- NO_JACK_PRESENCE_DETECT, ++ AZALIA_INTEGRATED, ++ AZALIA_LOCATION_OTHER, /* vendor: AZALIA_SEPARATE_CHASSIS */ ++ AZALIA_SPECIAL7, /* lid, vendor: AZALIA_GEOLOCATION_NA*/ ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0) + ), + + /* Integrated speakers, vendor value: 0x90170110 */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( +- INTEGRATED, +- LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */ +- BOTTOM, /* vendor: NA */ +- SPEAKER, +- OTHER_ANALOG, +- COLOR_UNKNOWN, +- NO_JACK_PRESENCE_DETECT, ++ AZALIA_INTEGRATED, ++ AZALIA_LOCATION_OTHER, /* vendor: AZALIA_SEPARATE_CHASSIS */ ++ AZALIA_BOTTOM, /* vendor: AZALIA_GEOLOCATION_NA*/ ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0) + ), + + /* Headphones, vendor value: 0x02211020 */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( +- JACK, +- EXTERNAL_PRIMARY_CHASSIS, +- RIGHT, /* vendor: FRONT */ +- HP_OUT, +- STEREO_MONO_1_8, +- BLACK, +- JACK_PRESENCE_DETECT, ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS, ++ AZALIA_RIGHT, /* vendor: AZALIA_FRONT */ ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, + 2, 0) + ), + + /* ext. Microphone, vendor value: 0x411111f0, linux override: 0x01a1913c */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( +- JACK, +- EXTERNAL_PRIMARY_CHASSIS, +- RIGHT, /* vendor: REAR */ +- MIC_IN, +- STEREO_MONO_1_8, +- BLACK, /* vendor: PINK */ +- NO_JACK_PRESENCE_DETECT, ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS, ++ AZALIA_RIGHT, /* vendor: AZALIA_REAR */ ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, /* vendor: AZALIA_PINK */ ++ AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 12) + ), + + /* PCBEEP, vendor value: 0x41748245 */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC( +- INTEGRATED, /* vendor: NC */ +- INTERNAL, /* vendor: EXTERNAL_PRIMARY_CHASSIS */ +- NA, /* vendor: REAR */ +- DEVICE_OTHER, /* vendor: MODEM_HANDSET_SIDE */ +- OTHER_ANALOG, /* vendor: RCA */ +- COLOR_UNKNOWN, /* vendor: PURPLE */ +- NO_JACK_PRESENCE_DETECT, /* vendor: 2 */ ++ AZALIA_INTEGRATED, /* vendor: AZALIA_NC */ ++ AZALIA_INTERNAL, /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS */ ++ AZALIA_GEOLOCATION_NA, /* vendor: AZALIA_REAR */ ++ AZALIA_DEVICE_OTHER, /* vendor: AZALIA_MODEM_HANDSET_SIDE */ ++ AZALIA_OTHER_ANALOG, /* vendor: AZALIA_RCA */ ++ AZALIA_COLOR_UNKNOWN, /* vendor: AZALIA_PURPLE */ ++ AZALIA_NO_JACK_PRESENCE_DETECT, /* vendor: 2 */ + 4, 5) + ), + +diff --git a/src/mainboard/siemens/chili/variants/chili/hda_verb.c b/src/mainboard/siemens/chili/variants/chili/hda_verb.c +index f0e403acd0..7fdb884465 100644 +--- a/src/mainboard/siemens/chili/variants/chili/hda_verb.c ++++ b/src/mainboard/siemens/chili/variants/chili/hda_verb.c +@@ -1,7 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + + #include +-#include + + const u32 cim_verb_data[] = { + /* coreboot specific header */ +@@ -15,31 +14,36 @@ const u32 cim_verb_data[] = { + AZALIA_SUBVENDOR(0, 0x110a4097), + + /* Pin Widget Verb Table */ +- AZALIA_PIN_CFG(0, 0x14, /* 0x14 Speaker OUT */ +- (AZALIA_PINCFG_PORT_FIXED << 30) | +- (AZALIA_PINCFG_LOCATION_INTERNAL << 24) | +- (AZALIA_PINCFG_DEVICE_SPEAKER << 20) | +- (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16) | +- (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) | +- (1 << 4) | 0 +- ), +- AZALIA_PIN_CFG(0, 0x21, /* 0x21 Headphone OUT */ +- (AZALIA_PINCFG_PORT_JACK << 30) | +- (AZALIA_PINCFG_LOCATION_FRONT << 24) | +- (AZALIA_PINCFG_DEVICE_HP_OUT << 20) | +- (AZALIA_PINCFG_CONN_COMBINATION << 16) | +- (AZALIA_PINCFG_COLOR_BLACK << 12) | +- (2 << 4) | 0 +- ), +- AZALIA_PIN_CFG(0, 0x19, /* 0x19 MIC2 */ +- (AZALIA_PINCFG_PORT_JACK << 30) | +- (AZALIA_PINCFG_LOCATION_FRONT << 24) | +- (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) | +- (AZALIA_PINCFG_CONN_COMBINATION << 16) | +- (AZALIA_PINCFG_COLOR_BLACK << 12) | +- (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) | +- (3 << 4) | 0 +- ), ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( /* 0x14 Speaker OUT */ ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_GEOLOCATION_NA, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( /* 0x21 Headphone OUT */ ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS, ++ AZALIA_FRONT, ++ AZALIA_HP_OUT, ++ AZALIA_COMBINATION, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( /* 0x19 MIC2 */ ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS, ++ AZALIA_FRONT, ++ AZALIA_MIC_IN, ++ AZALIA_COMBINATION, ++ AZALIA_BLACK, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* 0x12 Digital MIC */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(1)), /* 0x17 Mono OUT */ +@@ -61,13 +65,16 @@ const u32 cim_verb_data[] = { + 0x20878101, + AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_CFG_NC(1)), +- AZALIA_PIN_CFG(2, 0x07, +- (AZALIA_PINCFG_PORT_JACK << 30) | +- (AZALIA_PINCFG_LOCATION_REAR_PANEL << 24) | +- (AZALIA_PINCFG_DEVICE_DIGITAL_OUT << 20) | +- (AZALIA_PINCFG_CONN_OTHER_DIGITAL << 16) | +- (1 << 4) | 0 +- ), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS, ++ AZALIA_SPECIAL7, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), + /* Disable 2nd & 3rd pin widgets again */ + 0x20878100, + 0x20878100, +-- +2.39.5 + diff --git a/patches/coreboot-24.02.01/0007-include-device-azalia_device.h-Merge-location1-and-l.patch b/patches/coreboot-24.02.01/0007-include-device-azalia_device.h-Merge-location1-and-l.patch new file mode 100644 index 00000000..3115e2b5 --- /dev/null +++ b/patches/coreboot-24.02.01/0007-include-device-azalia_device.h-Merge-location1-and-l.patch @@ -0,0 +1,194 @@ +From 907aa8bfc5d1e87a5c269c34888aecdf4af3d6aa Mon Sep 17 00:00:00 2001 +From: Nicholas Sudsgaard +Date: Sun, 25 Feb 2024 09:32:33 +0900 +Subject: [PATCH 07/11] include/device/azalia_device.h: Merge location1 and + location2 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This changes the location to be expressed as a combination of ORs. This +allows aliases for special locations. + +For example, `AZALIA_REAR_PANEL` is easier to read than +`AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`. + +References: + - Intel High Definition Audio Specification, rev. 1.0a, page 180, + Table 110. Location. + +Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 +Signed-off-by: Nicholas Sudsgaard +Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740 +Tested-by: build bot (Jenkins) +Reviewed-by: Michael Niewöhner +Reviewed-by: Nico Huber +Reviewed-by: Felix Singer +--- + src/include/device/azalia_device.h | 36 +++++++++++-------- + .../clevo/tgl-u/variants/l140mu/hda_verb.c | 17 ++++----- + .../siemens/chili/variants/chili/hda_verb.c | 10 ++---- + 3 files changed, 32 insertions(+), 31 deletions(-) + +diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h +index 4d9298cf95..1fc0baf49b 100644 +--- a/src/include/device/azalia_device.h ++++ b/src/include/device/azalia_device.h +@@ -50,10 +50,10 @@ enum azalia_pin_connection { + }; + + enum azalia_pin_location_gross { +- AZALIA_EXTERNAL_PRIMARY_CHASSIS = 0x0, +- AZALIA_INTERNAL = 0x1, +- AZALIA_SEPARATE_CHASSIS = 0x2, +- AZALIA_LOCATION_OTHER = 0x3, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS = 0x00, ++ AZALIA_INTERNAL = 0x10, ++ AZALIA_SEPARATE_CHASSIS = 0x20, ++ AZALIA_LOCATION_OTHER = 0x30, + }; + + enum azalia_pin_location_geometric { +@@ -69,6 +69,16 @@ enum azalia_pin_location_geometric { + AZALIA_SPECIAL9 = 0x9, + }; + ++enum azalia_pin_location_special { ++ AZALIA_REAR_PANEL = AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_SPECIAL7, ++ AZALIA_DRIVE_BAY = AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_SPECIAL8, ++ AZALIA_RISER = AZALIA_INTERNAL | AZALIA_SPECIAL7, ++ AZALIA_DIGITAL_DISPLAY = AZALIA_INTERNAL | AZALIA_SPECIAL8, ++ AZALIA_ATAPI = AZALIA_INTERNAL | AZALIA_SPECIAL9, ++ AZALIA_MOBILE_LID_INSIDE = AZALIA_LOCATION_OTHER | AZALIA_SPECIAL7, ++ AZALIA_MOBILE_LID_OUTSIDE = AZALIA_LOCATION_OTHER | AZALIA_SPECIAL8, ++}; ++ + enum azalia_pin_device { + AZALIA_LINE_OUT = 0x0, + AZALIA_SPEAKER = 0x1, +@@ -123,16 +133,14 @@ enum azalia_pin_misc { + AZALIA_NO_JACK_PRESENCE_DETECT = 0x1, + }; + +-#define AZALIA_PIN_DESC(conn, location2, location1, dev, type, color, misc, \ +- association, sequence) \ +- ((((conn) << 30) & 0xc0000000) | \ +- (((location2) << 28) & 0x30000000) | \ +- (((location1) << 24) & 0x0f000000) | \ +- (((dev) << 20) & 0x00f00000) | \ +- (((type) << 16) & 0x000f0000) | \ +- (((color) << 12) & 0x0000f000) | \ +- (((misc) << 8) & 0x00000f00) | \ +- (((association) << 4) & 0x000000f0) | \ ++#define AZALIA_PIN_DESC(conn, location, dev, type, color, misc, association, sequence) \ ++ ((((conn) << 30) & 0xc0000000) | \ ++ (((location) << 24) & 0x3f000000) | \ ++ (((dev) << 20) & 0x00f00000) | \ ++ (((type) << 16) & 0x000f0000) | \ ++ (((color) << 12) & 0x0000f000) | \ ++ (((misc) << 8) & 0x00000f00) | \ ++ (((association) << 4) & 0x000000f0) | \ + (((sequence) << 0) & 0x0000000f)) + + #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ +diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +index 2e1a5799d7..db9da04235 100644 +--- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c ++++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +@@ -13,8 +13,7 @@ const u32 cim_verb_data[] = { + /* Microphone (display lid), vendor value: 0x90a60130 */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, +- AZALIA_LOCATION_OTHER, /* vendor: AZALIA_SEPARATE_CHASSIS */ +- AZALIA_SPECIAL7, /* lid, vendor: AZALIA_GEOLOCATION_NA*/ ++ AZALIA_MOBILE_LID_INSIDE, /* vendor: AZALIA_SEPARATE_CHASSIS */ + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, +@@ -25,8 +24,7 @@ const u32 cim_verb_data[] = { + /* Integrated speakers, vendor value: 0x90170110 */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, +- AZALIA_LOCATION_OTHER, /* vendor: AZALIA_SEPARATE_CHASSIS */ +- AZALIA_BOTTOM, /* vendor: AZALIA_GEOLOCATION_NA*/ ++ AZALIA_LOCATION_OTHER | AZALIA_BOTTOM, /* vendor: AZALIA_SEPARATE_CHASSIS */ + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, +@@ -37,8 +35,8 @@ const u32 cim_verb_data[] = { + /* Headphones, vendor value: 0x02211020 */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS, +- AZALIA_RIGHT, /* vendor: AZALIA_FRONT */ ++ /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT */ ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, +@@ -49,8 +47,8 @@ const u32 cim_verb_data[] = { + /* ext. Microphone, vendor value: 0x411111f0, linux override: 0x01a1913c */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS, +- AZALIA_RIGHT, /* vendor: AZALIA_REAR */ ++ /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR */ ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, /* vendor: AZALIA_PINK */ +@@ -61,8 +59,7 @@ const u32 cim_verb_data[] = { + /* PCBEEP, vendor value: 0x41748245 */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, /* vendor: AZALIA_NC */ +- AZALIA_INTERNAL, /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS */ +- AZALIA_GEOLOCATION_NA, /* vendor: AZALIA_REAR */ ++ AZALIA_INTERNAL, /* vendor: AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR */ + AZALIA_DEVICE_OTHER, /* vendor: AZALIA_MODEM_HANDSET_SIDE */ + AZALIA_OTHER_ANALOG, /* vendor: AZALIA_RCA */ + AZALIA_COLOR_UNKNOWN, /* vendor: AZALIA_PURPLE */ +diff --git a/src/mainboard/siemens/chili/variants/chili/hda_verb.c b/src/mainboard/siemens/chili/variants/chili/hda_verb.c +index 7fdb884465..b9748612a5 100644 +--- a/src/mainboard/siemens/chili/variants/chili/hda_verb.c ++++ b/src/mainboard/siemens/chili/variants/chili/hda_verb.c +@@ -17,7 +17,6 @@ const u32 cim_verb_data[] = { + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( /* 0x14 Speaker OUT */ + AZALIA_INTEGRATED, + AZALIA_INTERNAL, +- AZALIA_GEOLOCATION_NA, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, +@@ -26,8 +25,7 @@ const u32 cim_verb_data[] = { + )), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( /* 0x21 Headphone OUT */ + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS, +- AZALIA_FRONT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_COMBINATION, + AZALIA_BLACK, +@@ -36,8 +34,7 @@ const u32 cim_verb_data[] = { + )), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( /* 0x19 MIC2 */ + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS, +- AZALIA_FRONT, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_COMBINATION, + AZALIA_BLACK, +@@ -67,8 +64,7 @@ const u32 cim_verb_data[] = { + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_CFG_NC(1)), + AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, +- AZALIA_EXTERNAL_PRIMARY_CHASSIS, +- AZALIA_SPECIAL7, ++ AZALIA_REAR_PANEL, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, +-- +2.39.5 + diff --git a/patches/coreboot-24.02.01/0008-device-azalia-Separate-codec-checking-and-initializa.patch b/patches/coreboot-24.02.01/0008-device-azalia-Separate-codec-checking-and-initializa.patch new file mode 100644 index 00000000..b36b8a64 --- /dev/null +++ b/patches/coreboot-24.02.01/0008-device-azalia-Separate-codec-checking-and-initializa.patch @@ -0,0 +1,173 @@ +From 14b83c4c0500db7860f87fa5580accc12fef1110 Mon Sep 17 00:00:00 2001 +From: Nicholas Sudsgaard +Date: Fri, 2 Feb 2024 18:21:34 +0900 +Subject: [PATCH 08/11] device/azalia: Separate codec checking and + initialization + +This also changes how debug messages will be printed. I focused on +reducing clutter on the screen and made the style of the messages +consistent. + +Before: +azalia_audio: Initializing codec #5 + codec not ready. +azalia_audio: Initializing codec #4 + codec not valid. +azalia_audio: Initializing codec #3 +azalia_audio: viddid: ffffffff +azalia_audio: verb_size: 4 +azalia_audio: verb loaded. + +After: +azalia_audio: codec #5 not ready +azalia_audio: codec #4 not valid +azalia_audio: initializing codec #3... +azalia_audio: - vendor/device id: 0xffffffff +azalia_audio: - verb size: 4 +azalia_audio: - verb loaded + +Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 +Signed-off-by: Nicholas Sudsgaard +Reviewed-on: https://review.coreboot.org/c/coreboot/+/80332 +Reviewed-by: Nico Huber +Reviewed-by: Felix Singer +Tested-by: build bot (Jenkins) +--- + src/device/azalia_device.c | 67 ++++++++++++++++-------------- + src/include/device/azalia_device.h | 2 + + 2 files changed, 37 insertions(+), 32 deletions(-) + +diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c +index 4ac585dac1..8051f2e7ee 100644 +--- a/src/device/azalia_device.c ++++ b/src/device/azalia_device.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + int azalia_set_bits(void *port, u32 mask, u32 val) + { +@@ -97,7 +98,7 @@ no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); +- printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); ++ printk(BIOS_DEBUG, "azalia_audio: no codec!\n"); + return 0; + } + +@@ -226,55 +227,57 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) + { + } + +-void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes) ++static bool codec_is_operative(u8 *base, const int addr) + { +- u32 reg32; +- const u32 *verb; +- u32 verb_size; +- +- printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); +- +- /* 1 */ + if (wait_for_ready(base) < 0) { +- printk(BIOS_DEBUG, " codec not ready.\n"); +- return; ++ printk(BIOS_DEBUG, "azalia_audio: codec #%d not ready\n", addr); ++ return false; + } + +- reg32 = (addr << 28) | 0x000f0000; ++ const u32 reg32 = (addr << 28) | 0x000f0000; + write32(base + HDA_IC_REG, reg32); + + if (wait_for_valid(base) < 0) { +- printk(BIOS_DEBUG, " codec not valid.\n"); +- return; ++ printk(BIOS_DEBUG, "azalia_audio: codec #%d not valid\n", addr); ++ return false; + } ++ return true; ++} + +- /* 2 */ +- reg32 = read32(base + HDA_IR_REG); +- printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); +- verb_size = azalia_find_verb(verb_table, verb_table_bytes, reg32, &verb); ++void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes) ++{ ++ const u32 viddid = read32(base + HDA_IR_REG); ++ const u32 *verb; ++ u32 verb_size; ++ ++ printk(BIOS_DEBUG, "azalia_audio: initializing codec #%d...\n", addr); ++ printk(BIOS_DEBUG, "azalia_audio: - vendor/device id: 0x%08x\n", viddid); ++ ++ verb_size = azalia_find_verb(verb_table, verb_table_bytes, viddid, &verb); + +- if (!verb_size) { +- printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); ++ if (verb_size == 0) { ++ printk(BIOS_DEBUG, "azalia_audio: - no verb!\n"); + return; + } +- printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size); ++ printk(BIOS_DEBUG, "azalia_audio: - verb size: %u\n", verb_size); + +- /* 3 */ +- const int rc = azalia_program_verb_table(base, verb, verb_size); +- if (rc < 0) +- printk(BIOS_DEBUG, "azalia_audio: verb not loaded.\n"); ++ if (azalia_program_verb_table(base, verb, verb_size) < 0) ++ printk(BIOS_DEBUG, "azalia_audio: - verb not loaded\n"); + else +- printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); ++ printk(BIOS_DEBUG, "azalia_audio: - verb loaded\n"); + +- mainboard_azalia_program_runtime_verbs(base, reg32); ++ mainboard_azalia_program_runtime_verbs(base, viddid); + } + +-void azalia_codecs_init(u8 *base, u16 codec_mask) ++static bool codec_can_init(const u16 codec_mask, u8 *base, const int addr) + { +- int i; ++ return codec_mask & (1 << addr) && codec_is_operative(base, addr); ++} + +- for (i = 14; i >= 0; i--) { +- if (codec_mask & (1 << i)) ++void azalia_codecs_init(u8 *base, u16 codec_mask) ++{ ++ for (int i = AZALIA_MAX_CODECS - 1; i >= 0; i--) { ++ if (codec_can_init(codec_mask, base, i)) + azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size); + } + +@@ -298,7 +301,7 @@ void azalia_audio_init(struct device *dev) + codec_mask = codec_detect(base); + + if (codec_mask) { +- printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); ++ printk(BIOS_DEBUG, "azalia_audio: codec_mask = 0x%02x\n", codec_mask); + azalia_codecs_init(base, codec_mask); + } + } +diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h +index 1fc0baf49b..59e7ea2af3 100644 +--- a/src/include/device/azalia_device.h ++++ b/src/include/device/azalia_device.h +@@ -18,6 +18,8 @@ + #define HDA_ICII_BUSY (1 << 0) + #define HDA_ICII_VALID (1 << 1) + ++#define AZALIA_MAX_CODECS 15 ++ + int azalia_set_bits(void *port, u32 mask, u32 val); + int azalia_enter_reset(u8 *base); + int azalia_exit_reset(u8 *base); +-- +2.39.5 + diff --git a/patches/coreboot-24.02.01/0009-azalia-Get-rid-of-return-1-0.patch b/patches/coreboot-24.02.01/0009-azalia-Get-rid-of-return-1-0.patch new file mode 100644 index 00000000..252c8b4a --- /dev/null +++ b/patches/coreboot-24.02.01/0009-azalia-Get-rid-of-return-1-0.patch @@ -0,0 +1,301 @@ +From 9ed9e8655dde4df0692ca04f550ae2abd81d2b40 Mon Sep 17 00:00:00 2001 +From: Elyes Haouas +Date: Wed, 17 Jul 2024 12:22:43 +0200 +Subject: [PATCH 09/11] azalia: Get rid of "return {-1,0} + +Use 'enum cb_err' instead of {-1,0}. + +Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e +Signed-off-by: Elyes Haouas +Reviewed-on: https://review.coreboot.org/c/coreboot/+/83503 +Tested-by: build bot (Jenkins) +Reviewed-by: Martin L Roth +--- + src/device/azalia_device.c | 16 ++++++++-------- + src/include/device/azalia_device.h | 7 +++---- + src/soc/intel/common/hda_verb.c | 8 ++++---- + src/southbridge/intel/bd82x6x/azalia.c | 3 ++- + src/southbridge/intel/i82801gx/azalia.c | 7 ++++--- + src/southbridge/intel/i82801ix/azalia.c | 6 ++++-- + src/southbridge/intel/i82801jx/azalia.c | 6 ++++-- + src/southbridge/intel/ibexpeak/azalia.c | 4 +++- + src/southbridge/intel/lynxpoint/hda_verb.c | 7 ++++--- + 9 files changed, 36 insertions(+), 28 deletions(-) + +diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c +index 8051f2e7ee..e709d9fe20 100644 +--- a/src/device/azalia_device.c ++++ b/src/device/azalia_device.c +@@ -9,7 +9,7 @@ + #include + #include + +-int azalia_set_bits(void *port, u32 mask, u32 val) ++static enum cb_err azalia_set_bits(void *port, u32 mask, u32 val) + { + struct stopwatch sw; + u32 reg32; +@@ -32,17 +32,17 @@ int azalia_set_bits(void *port, u32 mask, u32 val) + + /* Timeout occurred */ + if (stopwatch_expired(&sw)) +- return -1; +- return 0; ++ return CB_ERR; ++ return CB_SUCCESS; + } + +-int azalia_enter_reset(u8 *base) ++enum cb_err azalia_enter_reset(u8 *base) + { + /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ + return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); + } + +-int azalia_exit_reset(u8 *base) ++enum cb_err azalia_exit_reset(u8 *base) + { + /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST); +@@ -53,7 +53,7 @@ static u16 codec_detect(u8 *base) + struct stopwatch sw; + u16 reg16; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + if (CONFIG(AZALIA_LOCK_DOWN_R_WO_GCAP)) { +@@ -80,10 +80,10 @@ static u16 codec_detect(u8 *base) + if (stopwatch_expired(&sw)) + goto no_codec; + +- if (azalia_enter_reset(base) < 0) ++ if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0x0e)[14:0] */ +diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h +index 59e7ea2af3..7fe6514ed2 100644 +--- a/src/include/device/azalia_device.h ++++ b/src/include/device/azalia_device.h +@@ -6,7 +6,7 @@ + #include + #include + #include +-#include ++#include + + #define HDA_GCAP_REG 0x00 + #define HDA_GCTL_REG 0x08 +@@ -20,9 +20,8 @@ + + #define AZALIA_MAX_CODECS 15 + +-int azalia_set_bits(void *port, u32 mask, u32 val); +-int azalia_enter_reset(u8 *base); +-int azalia_exit_reset(u8 *base); ++enum cb_err azalia_enter_reset(u8 *base); ++enum cb_err azalia_exit_reset(u8 *base); + u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb); + int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size); + void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes); +diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c +index dceb03183e..67a8f24516 100644 +--- a/src/soc/intel/common/hda_verb.c ++++ b/src/soc/intel/common/hda_verb.c +@@ -4,7 +4,7 @@ + #include + #include + #include +-#include ++#include + + #include "hda_verb.h" + +@@ -13,7 +13,7 @@ int hda_codec_detect(u8 *base) + u8 reg8; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Write back the value once reset bit is set. */ +@@ -26,11 +26,11 @@ int hda_codec_detect(u8 *base) + write8(base + HDA_STATESTS_REG, 0xf); + + /* Turn off the link and poll RESET# bit until it reads back as 0 */ +- if (azalia_enter_reset(base) < 0) ++ if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Turn on the link and poll RESET# bit until it reads back as 1 */ +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ +diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c +index ddaa8a1bb0..4eeb3b5cf4 100644 +--- a/src/southbridge/intel/bd82x6x/azalia.c ++++ b/src/southbridge/intel/bd82x6x/azalia.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + #include "chip.h" + #include "pch.h" +@@ -16,7 +17,7 @@ static int codec_detect(u8 *base) + { + u8 reg8; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Write back the value once reset bit is set. */ +diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c +index 31827e6de9..cef3dee191 100644 +--- a/src/southbridge/intel/i82801gx/azalia.c ++++ b/src/southbridge/intel/i82801gx/azalia.c +@@ -8,7 +8,8 @@ + #include + #include + #include +-#include ++#include ++ + #include "chip.h" + #include "i82801gx.h" + +@@ -16,10 +17,10 @@ static int codec_detect(u8 *base) + { + u32 reg32; + +- if (azalia_enter_reset(base) < 0) ++ if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ +diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c +index fdc951472e..228b188f89 100644 +--- a/src/southbridge/intel/i82801ix/azalia.c ++++ b/src/southbridge/intel/i82801ix/azalia.c +@@ -7,6 +7,8 @@ + #include + #include + #include ++#include ++ + #include "chip.h" + #include "i82801ix.h" + +@@ -14,10 +16,10 @@ static int codec_detect(u8 *base) + { + u32 reg32; + +- if (azalia_enter_reset(base) < 0) ++ if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ +diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c +index fa0209ae78..6b840e7d50 100644 +--- a/src/southbridge/intel/i82801jx/azalia.c ++++ b/src/southbridge/intel/i82801jx/azalia.c +@@ -7,6 +7,8 @@ + #include + #include + #include ++#include ++ + #include "chip.h" + #include "i82801jx.h" + +@@ -14,10 +16,10 @@ static int codec_detect(u8 *base) + { + u32 reg32; + +- if (azalia_enter_reset(base) < 0) ++ if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ +diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c +index ac950c46df..6196096a14 100644 +--- a/src/southbridge/intel/ibexpeak/azalia.c ++++ b/src/southbridge/intel/ibexpeak/azalia.c +@@ -8,13 +8,15 @@ + #include + #include + #include ++#include ++ + #include "pch.h" + + static int codec_detect(u8 *base) + { + u8 reg8; + +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Write back the value once reset bit is set. */ +diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c +index 7e9f4d2c48..e79b5d1b20 100644 +--- a/src/southbridge/intel/lynxpoint/hda_verb.c ++++ b/src/southbridge/intel/lynxpoint/hda_verb.c +@@ -3,6 +3,7 @@ + #include + #include + #include ++#include + + #include "hda_verb.h" + +@@ -11,7 +12,7 @@ int hda_codec_detect(u8 *base) + u8 reg8; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Write back the value once reset bit is set. */ +@@ -24,11 +25,11 @@ int hda_codec_detect(u8 *base) + write8(base + HDA_STATESTS_REG, 0xf); + + /* Turn off the link and poll RESET# bit until it reads back as 0 */ +- if (azalia_enter_reset(base) < 0) ++ if (azalia_enter_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Turn on the link and poll RESET# bit until it reads back as 1 */ +- if (azalia_exit_reset(base) < 0) ++ if (azalia_exit_reset(base) != CB_SUCCESS) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ +-- +2.39.5 + diff --git a/patches/coreboot-24.02.01/0010-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/patches/coreboot-24.02.01/0010-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch new file mode 100644 index 00000000..b8ce60a3 --- /dev/null +++ b/patches/coreboot-24.02.01/0010-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch @@ -0,0 +1,30 @@ +From a8dd041e06aadb959dfe14ddeaf938bdd9700d3a Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Fri, 22 Nov 2024 21:26:48 +0000 +Subject: [PATCH 10/11] soc/intel/skylake: Enable 4E/4F PNP I/O ports in + bootblock + +Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173 +Signed-off-by: Mate Kukri +--- + src/soc/intel/skylake/bootblock/pch.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c +index cc2d384e2e..4b0bf310df 100644 +--- a/src/soc/intel/skylake/bootblock/pch.c ++++ b/src/soc/intel/skylake/bootblock/pch.c +@@ -99,8 +99,8 @@ static void soc_config_pwrmbase(void) + + void pch_early_iorange_init(void) + { +- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | +- LPC_IOE_EC_62_66; ++ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | ++ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66; + + const config_t *config = config_of_soc(); + +-- +2.39.5 + diff --git a/patches/coreboot-24.02.01/0011-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/patches/coreboot-24.02.01/0011-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch new file mode 100644 index 00000000..9fe28dab --- /dev/null +++ b/patches/coreboot-24.02.01/0011-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch @@ -0,0 +1,2237 @@ +From 76fae5a1b0c7cf5412de1caf549a4019e4935a00 Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Tue, 31 Dec 2024 22:49:15 +0000 +Subject: [PATCH 11/11] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s + +These machine have BootGuard fused and requires deguard to +boot coreboot. + +Known issues: +- Alpine Ridge Thunderbolt 3 controller does not work +- Some Fn+F{1-12} keys aren't handled correctly +- Nvidia dGPU is finicky + - Needs option ROM + - Power enable code is buggy + - Nouveau only works on linux 6.8-6.9 +- Headphone jack isn't detected as plugged in despite correct verbs + +Thanks to Leah Rowe for helping with the T480s. + +Signed-off-by: Mate Kukri +Change-Id: I19d421412c771c1f242f6ff39453f824fa866163 +--- + src/device/pci_rom.c | 4 +- + src/ec/lenovo/h8/acpi/ec.asl | 2 +- + src/ec/lenovo/h8/bluetooth.c | 6 +- + src/ec/lenovo/h8/wwan.c | 6 +- + src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++ + .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 + + .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++ + .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++ + .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 + + .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++ + .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++ + src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++ + src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++ + src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++ + src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 + + .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++ + .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes + .../variants/t480/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++ + .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++ + .../variants/t480/memory_init_params.c | 20 ++ + .../variants/t480/overridetree.cb | 103 +++++++++ + .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes + .../variants/t480s/gma-mainboard.ads | 19 ++ + .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++ + .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++ + .../variants/t480s/memory_init_params.c | 44 ++++ + .../variants/t480s/overridetree.cb | 103 +++++++++ + .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes + .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes + 49 files changed, 1583 insertions(+), 6 deletions(-) + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin + create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin + +diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c +index 1e212ab216..83f44bec05 100644 +--- a/src/device/pci_rom.c ++++ b/src/device/pci_rom.c +@@ -313,11 +313,13 @@ void pci_rom_ssdt(const struct device *device) + return; + } + ++#if 0 + const char *scope = acpi_device_path(device); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device)); + return; + } ++#endif + + /* Supports up to four devices. */ + if ((CBMEM_ID_ROM0 + ngfx) > CBMEM_ID_ROM3) { +@@ -345,7 +347,7 @@ void pci_rom_ssdt(const struct device *device) + memcpy(cbrom, rom, cbrom_length); + + /* write _ROM method */ +- acpigen_write_scope(scope); ++ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP"); + acpigen_write_rom(cbrom, cbrom_length); + acpigen_pop_len(); /* pop scope */ + } +diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl +index bc54d3b422..8f4a8e1986 100644 +--- a/src/ec/lenovo/h8/acpi/ec.asl ++++ b/src/ec/lenovo/h8/acpi/ec.asl +@@ -331,7 +331,7 @@ Device(EC) + #include "sleepbutton.asl" + #include "lid.asl" + #include "beep.asl" +-#include "thermal.asl" ++//#include "thermal.asl" + #include "systemstatus.asl" + #include "thinkpad.asl" + } +diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c +index 16fc8dce39..be71a24ced 100644 +--- a/src/ec/lenovo/h8/bluetooth.c ++++ b/src/ec/lenovo/h8/bluetooth.c +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +-#include ++// #include + #include + #include + #include +@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev) + { + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (!conf->has_bdc_detection) { ++ if (1 || !conf->has_bdc_detection) { + printk(BIOS_INFO, "H8: BDC detection not implemented. " + "Assuming BDC installed\n"); + return true; + } + ++#if 0 + if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) { + printk(BIOS_INFO, "H8: BDC installed\n"); + return true; + } ++#endif + + printk(BIOS_INFO, "H8: BDC not installed\n"); + return false; +diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c +index 685886fcce..5cdcf77406 100644 +--- a/src/ec/lenovo/h8/wwan.c ++++ b/src/ec/lenovo/h8/wwan.c +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +-#include ++// #include + #include + #include + #include +@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev) + { + struct ec_lenovo_h8_config *conf = dev->chip_info; + +- if (!conf->has_wwan_detection) { ++ if (1 || !conf->has_wwan_detection) { + printk(BIOS_INFO, "H8: WWAN detection not implemented. " + "Assuming WWAN installed\n"); + return true; + } + ++#if 0 + if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) { + printk(BIOS_INFO, "H8: WWAN installed\n"); + return true; + } ++#endif + + printk(BIOS_INFO, "H8: WWAN not installed\n"); + return false; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +new file mode 100644 +index 0000000000..4998672943 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +@@ -0,0 +1,57 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ bool ++ select BOARD_ROMSIZE_KB_16384 ++ select EC_LENOVO_H8 ++ select EC_LENOVO_PMH7 ++ select H8_HAS_BAT_THRESHOLDS_IMPL ++ select H8_HAS_LEDLOGO ++ select H8_HAS_PRIMARY_FN_KEYS ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM2 ++ select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM ++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB ++ select SOC_INTEL_KABYLAKE ++ select SPD_READ_BY_WORD ++ select SYSTEM_TYPE_LAPTOP ++ ++config BOARD_LENOVO_T480 ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ ++config BOARD_LENOVO_T480S ++ bool ++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ ++if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON ++ ++config MAINBOARD_DIR ++ default "lenovo/sklkbl_thinkpad" ++ ++config VARIANT_DIR ++ default "t480" if BOARD_LENOVO_T480 ++ default "t480s" if BOARD_LENOVO_T480S ++ ++config OVERRIDE_DEVICETREE ++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" ++ ++config MAINBOARD_PART_NUMBER ++ default "T480" if BOARD_LENOVO_T480 ++ default "T480s" if BOARD_LENOVO_T480S ++ ++config CBFS_SIZE ++ default 0x900000 ++ ++config DIMM_MAX ++ default 2 ++ ++config DIMM_SPD_SIZE ++ default 512 # DDR4 ++ ++endif +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +new file mode 100644 +index 0000000000..abc273f387 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config BOARD_LENOVO_T480 ++ bool "ThinkPad T480" ++ ++config BOARD_LENOVO_T480S ++ bool "ThinkPad T480s" +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk +new file mode 100644 +index 0000000000..c308239177 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk +@@ -0,0 +1,73 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++bootblock-y += bootblock.c ec.c ++ ++romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c ++ ++ramstage-y += ramstage.c ec.c ++ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads ++ ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin ++spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin ++spd_0.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin ++spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin ++spd_1.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin ++spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin ++spd_2.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin ++spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin ++spd_3.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin ++spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin ++spd_4.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin ++spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin ++spd_5.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin ++spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin ++spd_6.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin ++spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin ++spd_7.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin ++spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin ++spd_8.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin ++spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin ++spd_9.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin ++spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin ++spd_10.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin ++spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin ++spd_11.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin ++spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin ++spd_12.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin ++spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin ++spd_13.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin ++spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin ++spd_14.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin ++spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin ++spd_15.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin ++spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin ++spd_16.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin ++spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin ++spd_17.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin ++spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin ++spd_18.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin ++spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin ++spd_19.bin-type := raw ++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin ++spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin ++spd_20.bin-type := raw +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl +new file mode 100644 +index 0000000000..3a949a2fca +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++#define THINKPAD_EC_GPE 22 ++ ++Name(\TCRT, 100) ++Name(\TPSV, 90) ++Name(\FLVL, 0) ++ ++#include ++#include +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c +new file mode 100644 +index 0000000000..fb660dbdfa +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c +@@ -0,0 +1,60 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include "ec.h" ++ ++static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno) ++{ ++ microchip_pnp_enter_conf_state(port); ++ ++ // Select LPC I/F LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); ++ // Write UART BAR ++ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707); ++ // Set SIRQ4 to UART ++ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART); ++ ++ // Configure UART LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_UART); ++ pnp_write(port, UART_ACTIVATE, 0x01); ++ pnp_write(port, UART_CONFIG_SELECT, 0x00); ++ ++ microchip_pnp_exit_conf_state(port); ++ ++#ifdef CONFIG_BOARD_LENOVO_T480 ++ // Supply debug unlock key ++ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key); ++ ++ // Use debug writes to set UART_TX and UART_RX GPIOs ++ debug_write_dword(0xf0c400 + 0x110, 0x00001000); ++ debug_write_dword(0xf0c400 + 0x114, 0x00001000); ++#endif ++} ++ ++ ++#define UART_PORT 0x3f8 ++#define UART_IRQ 4 ++ ++void bootblock_mainboard_early_init(void) ++{ ++ // Tell EC via BIOS Debug Port 1 that the world isn't on fire ++ ++ // Let the EC know that BIOS code is running ++ outb(0x11, 0x86); ++ outb(0x6e, 0x86); ++ ++ // Enable accesses to EC1 interface ++ ec0_write(0, ec0_read(0) | 0x20); ++ ++ // Reset LEDs to power on state ++ // (Without this warm reboot leaves LEDs off) ++ ec0_write(0x0c, 0x80); ++ ec0_write(0x0c, 0x07); ++ ec0_write(0x0c, 0x8a); ++ ++ // Setup debug UART ++ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb +new file mode 100644 +index 0000000000..c07d4d53ca +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ # IGD Displays ++ register "gfx" = "GMA_STATIC_DISPLAYS(0)" ++ ++ register "panel_cfg" = "{ ++ .up_delay_ms = 200, ++ .down_delay_ms = 50, ++ .cycle_delay_ms = 600, ++ .backlight_on_delay_ms = 1, ++ .backlight_off_delay_ms = 200, ++ .backlight_pwm_hz = 200, ++ }" ++ ++ # Power ++ register "PmConfigSlpS3MinAssert" = "2" # 50ms ++ register "PmConfigSlpS4MinAssert" = "1" # 1s ++ register "PmConfigSlpSusMinAssert" = "3" # 500ms ++ register "PmConfigSlpAMinAssert" = "3" # 2s ++ ++ device domain 0 on ++ device ref igpu on end ++ device ref sa_thermal on end ++ device ref thermal on end ++ device ref south_xhci on end ++ device ref lpc_espi on ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ register "gen1_dec" = "0x007c1601" ++ register "gen2_dec" = "0x000c15e1" ++ ++ chip ec/lenovo/pmh7 ++ register "backlight_enable" = "true" ++ register "dock_event_enable" = "true" ++ device pnp ff.1 on end # dummy ++ end ++ ++ chip ec/lenovo/h8 ++ register "beepmask0" = "0x00" ++ register "beepmask1" = "0x86" ++ register "config0" = "0xa6" ++ register "config1" = "0x0d" ++ register "config2" = "0xa8" ++ register "config3" = "0xc4" ++ register "has_keyboard_backlight" = "1" ++ register "event2_enable" = "0xff" ++ register "event3_enable" = "0xff" ++ register "event4_enable" = "0xd0" ++ register "event5_enable" = "0x3c" ++ register "event7_enable" = "0x01" ++ register "event8_enable" = "0x7b" ++ register "event9_enable" = "0xff" ++ register "eventc_enable" = "0xff" ++ register "eventd_enable" = "0xff" ++ register "evente_enable" = "0x9d" ++ device pnp ff.2 on # dummy ++ io 0x60 = 0x62 ++ io 0x62 = 0x66 ++ io 0x64 = 0x1600 ++ io 0x66 = 0x1604 ++ end ++ end ++ ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end ++ end ++ device ref hda on end ++ end ++end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl +new file mode 100644 +index 0000000000..aa4d4de2a6 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 ++) ++{ ++ #include ++ #include ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ #include ++ } ++ ++ Scope (\_SB.PCI0.RP01) ++ { ++ Device (PEGP) ++ { ++ Name (_ADR, Zero) ++ } ++ } ++ ++ #include ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c +new file mode 100644 +index 0000000000..adb6a60324 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c +@@ -0,0 +1,153 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "ec.h" ++ ++#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55 ++#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa ++ ++void microchip_pnp_enter_conf_state(uint16_t port) ++{ ++ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port); ++} ++ ++void microchip_pnp_exit_conf_state(uint16_t port) ++{ ++ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port); ++} ++ ++uint8_t pnp_read(uint16_t port, uint8_t index) ++{ ++ outb(index, port); ++ return inb(port + 1); ++} ++ ++uint32_t pnp_read_le32(uint16_t port, uint8_t index) ++{ ++ return (uint32_t) pnp_read(port, index) | ++ (uint32_t) pnp_read(port, index + 1) << 8 | ++ (uint32_t) pnp_read(port, index + 2) << 16 | ++ (uint32_t) pnp_read(port, index + 3) << 24; ++} ++ ++void pnp_write(uint16_t port, uint8_t index, uint8_t value) ++{ ++ outb(index, port); ++ outb(value, port + 1); ++} ++ ++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value) ++{ ++ pnp_write(port, index, value & 0xff); ++ pnp_write(port, index + 1, value >> 8 & 0xff); ++ pnp_write(port, index + 2, value >> 16 & 0xff); ++ pnp_write(port, index + 3, value >> 24 & 0xff); ++} ++ ++static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (inb(cmd_port) & EC_OBF) ++ inb(data_port); ++} ++ ++static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (inb(cmd_port) & EC_IBF) ++ ; ++} ++ ++static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port) ++{ ++ while (!(inb(cmd_port) & EC_OBF)) ++ ; ++} ++ ++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr) ++{ ++ ecN_clear_out_queue(cmd_port, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(EC_READ, cmd_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(addr, data_port); ++ ecN_wait_to_recv(cmd_port, data_port); ++ return inb(data_port); ++} ++ ++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val) ++{ ++ ecN_clear_out_queue(cmd_port, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(EC_WRITE, cmd_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(addr, data_port); ++ ecN_wait_to_send(cmd_port, data_port); ++ outb(val, data_port); ++} ++ ++uint8_t eeprom_read(uint16_t addr) ++{ ++ ecN_clear_out_queue(EC2_CMD, EC2_DATA); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(1, EC2_CMD); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(addr, EC2_DATA); ++ ecN_wait_to_recv(EC2_CMD, EC2_DATA); ++ return inl(EC2_DATA); ++} ++ ++void eeprom_write(uint16_t addr, uint8_t val) ++{ ++ ecN_clear_out_queue(EC2_CMD, EC2_DATA); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl(2, EC2_CMD); ++ ecN_wait_to_send(EC2_CMD, EC2_DATA); ++ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA); ++ ecN_wait_to_recv(EC2_CMD, EC2_DATA); ++ inl(EC2_DATA); ++} ++ ++uint16_t debug_loaded_keys(void) ++{ ++ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86); ++} ++ ++static void debug_cmd(uint8_t cmd) ++{ ++ ec0_write(EC_DEBUG_CMD, cmd); ++ while (ec0_read(EC_DEBUG_CMD) & 0x80) ++ ; ++} ++ ++void debug_read_key(uint8_t i, uint8_t *key) ++{ ++ debug_cmd(0x80 | (i & 0xf)); ++ for (int j = 0; j < 8; ++j) ++ key[j] = ec0_read(0x3e + j); ++} ++ ++void debug_write_key(uint8_t i, const uint8_t *key) ++{ ++ for (int j = 0; j < 8; ++j) ++ ec0_write(0x3e + j, key[j]); ++ debug_cmd(0xc0 | (i & 0xf)); ++} ++ ++uint32_t debug_read_dword(uint32_t addr) ++{ ++ ecN_clear_out_queue(EC3_CMD, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(addr << 8 | 0xE2, EC3_DATA); ++ ecN_wait_to_recv(EC3_CMD, EC3_DATA); ++ return inl(EC3_DATA); ++} ++ ++void debug_write_dword(uint32_t addr, uint32_t val) ++{ ++ ecN_clear_out_queue(EC3_CMD, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(addr << 8 | 0xEA, EC3_DATA); ++ ecN_wait_to_send(EC3_CMD, EC3_DATA); ++ outl(val, EC3_DATA); ++} ++ ++const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf }; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h +new file mode 100644 +index 0000000000..d2963c8962 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h +@@ -0,0 +1,99 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef SKLKBL_THINKPAD_EC_H ++#define SKLKBL_THINKPAD_EC_H ++ ++// EC configuration base address ++#define EC_CFG_PORT 0x4e ++ ++// Chip global registers ++#define PNP_LDN_SELECT 0x07 ++# define LDN_UART 0x07 ++# define LDN_LPCIF 0x0c ++#define EC_DEVICE_ID 0x20 ++#define EC_DEVICE_REV 0x21 ++ ++// LPC I/F registers ++#define LPCIF_SIRQ(i) (0x40 + (i)) ++ ++#define LPCIF_BAR_CFG 0x60 ++#define LPCIF_BAR_MAILBOX 0x64 ++#define LPCIF_BAR_8042 0x68 ++#define LPCIF_BAR_ACPI_EC0 0x6c ++#define LPCIF_BAR_ACPI_EC1 0x70 ++#define LPCIF_BAR_ACPI_EC2 0x74 ++#define LPCIF_BAR_ACPI_EC3 0x78 ++#define LPCIF_BAR_ACPI_PM0 0x7c ++#define LPCIF_BAR_UART 0x80 ++#define LPCIF_BAR_FAST_KYBD 0x84 ++#define LPCIF_BAR_EMBED_FLASH 0x88 ++#define LPCIF_BAR_GP_SPI 0x8c ++#define LPCIF_BAR_EMI 0x90 ++#define LPCIF_BAR_PMH7 0x94 ++#define LPCIF_BAR_PORT80_DBG0 0x98 ++#define LPCIF_BAR_PORT80_DBG1 0x9c ++#define LPCIF_BAR_RTC 0xa0 ++ ++// UART registers ++#define UART_ACTIVATE 0x30 ++#define UART_CONFIG_SELECT 0xf0 ++ ++void microchip_pnp_enter_conf_state(uint16_t port); ++void microchip_pnp_exit_conf_state(uint16_t port); ++uint8_t pnp_read(uint16_t port, uint8_t index); ++uint32_t pnp_read_le32(uint16_t port, uint8_t index); ++void pnp_write(uint16_t port, uint8_t index, uint8_t value); ++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value); ++ ++#define EC0_CMD 0x0066 ++#define EC0_DATA 0x0062 ++#define EC1_CMD 0x1604 ++#define EC1_DATA 0x1600 ++#define EC2_CMD 0x1634 ++#define EC2_DATA 0x1630 ++#define EC3_CMD 0x161c ++#define EC3_DATA 0x1618 ++ ++#define EC_OBF (1 << 0) ++#define EC_IBF (1 << 1) ++ ++#define EC_READ 0x80 ++#define EC_WRITE 0x81 ++ ++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr); ++ ++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val); ++ ++// EC0 and EC1 mostly are useful with the READ/WRITE commands ++#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr) ++#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val) ++#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr) ++#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val) ++ ++// Read from the emulated EEPROM ++uint8_t eeprom_read(uint16_t addr); ++ ++// Write to the emulated EEPROM ++void eeprom_write(uint16_t addr, uint8_t val); ++ ++// Read loaded debug key mask ++uint16_t debug_loaded_keys(void); ++ ++// The following location (via either EC0 or EC1) can be used to interact with the debug interface ++#define EC_DEBUG_CMD 0x3d ++ ++void debug_read_key(uint8_t i, uint8_t *key); ++ ++void debug_write_key(uint8_t i, const uint8_t *key); ++ ++uint32_t debug_read_dword(uint32_t addr); ++ ++void debug_write_dword(uint32_t addr, uint32_t val); ++ ++// RW unlock key index ++#define DEBUG_RW_KEY_IDX 1 ++ ++// RW unlock key for EC version N24HT37W ++extern const uint8_t debug_rw_key[8]; ++ ++#endif +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h +new file mode 100644 +index 0000000000..d89ed712d4 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h +@@ -0,0 +1,8 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef GPIO_H ++#define GPIO_H ++ ++void variant_config_gpios(void); ++ ++#endif +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c +new file mode 100644 +index 0000000000..44c8578852 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c +@@ -0,0 +1,105 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "ec.h" ++#include "gpio.h" ++ ++#define GPIO_GPU_RST GPP_E22 // active low ++#define GPIO_1R8VIDEO_AON_ON GPP_E23 ++ ++#define GPIO_DGFX_PWRGD GPP_F3 ++ ++#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low ++#define GPIO_DGFX_VRAM_ID0 GPP_D11 ++#define GPIO_DGFX_VRAM_ID1 GPP_D12 ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" }; ++ ++ int dgfx_vram_id; ++ ++ // Setup GPIOs ++ variant_config_gpios(); ++ ++ // Detect and enable dGPU ++ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low ++ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1; ++ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]); ++ ++ // NOTE: i pulled this GPU enable sequence from thin air ++ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default. ++ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels ++ if (get_uint_option("dgpu_enable", 0)) { ++ printk(BIOS_DEBUG, "Enabling discrete GPU\n"); ++ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail ++ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU ++ ; ++ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset ++ } else { ++ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n"); ++ } ++ ++ } else { ++ printk(BIOS_DEBUG, "Discrete GPU not present\n"); ++ } ++} ++ ++static void dump_ec_cfg(uint16_t port) ++{ ++ microchip_pnp_enter_conf_state(port); ++ ++ // Device info ++ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID)); ++ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV)); ++ ++ // Switch to LPCIF LDN ++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF); ++ ++ // Dump SIRQs ++ for (int i = 0; i <= 15; i += 1) ++ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i))); ++ ++ // Dump BARs ++ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG)); ++ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX)); ++ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2)); ++ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3)); ++ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0)); ++ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART)); ++ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD)); ++ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH)); ++ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI)); ++ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI)); ++ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7)); ++ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0)); ++ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1)); ++ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC)); ++ ++ microchip_pnp_exit_conf_state(port); ++} ++ ++static void mainboard_enable(struct device *dev) ++{ ++ if (CONFIG(VGA_ROM_RUN)) ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++static void mainboard_init(void *chip_info) ++{ ++ dump_ec_cfg(EC_CFG_PORT); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++ .init = mainboard_init, ++}; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3 +GIT binary patch +literal 4106 +zcmeHJU2GIp6h5=FKeKmc=rAo()>4l^U|XP_ZDGYy!|YE>mu}hZ4|PdQy1bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+ +z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr +zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^LXW8| +z-Vsanq!Y==Kq9plQ+*gu^hf&pJ9?tY{h01cbtR&SfsVM!_*!D4W5>papLuo?gRur| +zF$`lX;f2t48Dpd4V@(*z=dq95OkkfiVU53N<(gE+=U)KHEdU4}@R=aMjTTTOcb8-a +zC9IXSxZB*|#u~SlHnpsY25L#Sxy6ljl16gI)H0f>for?qaszCX;ESpG=pqROFWR~Z +zTqQzcH(berra`9K(R~0OJ_eeA=> +z&R-)LYP^U3@%6h}+0)7m-mEOhOM92l32>zpvu-&@ZkPf<>~Bsv&Oy1O(`pbLUf3vt*0HIRk0U3EzI +zIeSaIE9*jps%6qP7$EQo8=K#f^K_mFpy5prkNNSOU;oI@KK0}Ge*G6eyWz+6OyADf +zE`}Db#-81u-uS=OJB*=`v}WPMs@ugdtLtbZo6OEUf}>!QL` +z1zQ!pLt!Zek0|;p3VTDrj}`q(g?+8yuZk|KY?X>TRlP@LPpbH`s-ITbSygS+Jq6cQ +zp|Em=T_#B53Y|R}mtw!K3mUyWRhytxx_wi^(}HurDkx@L%OlKIA%rq@7%bE{p{Wl~ +zJJ%lV6&>fxBjnbA8G(&P?a8o%P#c~Wo$7|%1UE-$r;6jwt1uejOfMLwF-BDgC-Q+N +za!Hx;1S&$9!rlNCTsI*IMZ0#Y5aEO7sjIz#jb`S|q7OpRYx`h&=PK}_YnN#poNF=7 +z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA +z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j +z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c +new file mode 100644 +index 0000000000..f7c29e1f39 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c +@@ -0,0 +1,203 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "../../gpio.h" ++ ++/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style ++ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */ ++ ++static const struct pad_config gpio_table[] = { ++ ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), ++ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), ++ PAD_NC(GPP_A19, NONE), ++ PAD_NC(GPP_A20, NONE), ++ PAD_NC(GPP_A21, NONE), ++ PAD_NC(GPP_A22, NONE), ++ PAD_NC(GPP_A23, NONE), ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_NC(GPP_B0, NONE), ++ PAD_NC(GPP_B1, NONE), ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */ ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */ ++ PAD_NC(GPP_B11, NONE), ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_NC(GPP_C2, NONE), ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ ++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ ++ PAD_NC(GPP_D10, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_NC(GPP_E0, NONE), ++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */ ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_NC(GPP_E5, NONE), ++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ ++ PAD_NC(GPP_E7, NONE), ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_NC(GPP_E19, NONE), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ ++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_NC(GPP_F0, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ ++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */ ++ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ ++ PAD_NC(GPP_F16, NONE), ++ PAD_NC(GPP_F17, NONE), ++ PAD_NC(GPP_F18, NONE), ++ PAD_NC(GPP_F19, NONE), ++ PAD_NC(GPP_F20, NONE), ++ PAD_NC(GPP_F21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), ++ PAD_NC(GPP_G1, NONE), ++ PAD_NC(GPP_G2, NONE), ++ PAD_NC(GPP_G3, NONE), ++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c +new file mode 100644 +index 0000000000..3a951ce0da +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa225d, // Subsystem ID ++ 11, ++ AZALIA_SUBVENDOR(0, 0x17aa225d), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c +new file mode 100644 +index 0000000000..5252a402f9 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ ++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for memory slots */ ++ struct spd_block blk = { .addr_map = { 0x50, 0x51, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +new file mode 100644 +index 0000000000..bf66bd3a69 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb +@@ -0,0 +1,103 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC1), // USB-A ++ [1] = USB2_PORT_MID(OC0), // USB-A (always on) ++ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port) ++ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC1), // USB-A ++ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port) ++ }" ++ end ++ ++ device ref sata on ++ # SATA_2 - JHDD1 SATA SSD ++ register "SataPortsEnable[2]" = "1" ++ register "SataPortsDevSlp[2]" = "1" ++ end ++ ++ # PCIe controller 1 - 1x4 ++ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0 ++ # ++ # PCIe controller 2 - 2x1+1x2 (lane reversal) ++ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8) ++ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2 ++ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3 ++ # ++ # PCIe controller 3 - 2x2 ++ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4 ++ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5 ++ ++ # dGPU - x4 ++ device ref pcie_rp1 on ++ register "PcieRpEnable[0]" = "1" ++ register "PcieRpClkReqSupport[0]" = "1" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "1" ++ register "PcieRpLtrEnable[0]" = "1" ++ end ++ ++ # Ethernet (clobbers RP8) ++ device ref gbe on ++ register "LanClkReqSupported" = "1" ++ register "LanClkReqNumber" = "1" ++ register "EnableLanLtr" = "1" ++ register "EnableLanK1Off" = "1" ++ end ++ ++ # M.2 WLAN - x1 ++ device ref pcie_rp7 on ++ register "PcieRpEnable[6]" = "1" ++ register "PcieRpClkReqSupport[6]" = "1" ++ register "PcieRpClkReqNumber[6]" = "2" ++ register "PcieRpClkSrcNumber[6]" = "2" ++ register "PcieRpAdvancedErrorReporting[6]" = "1" ++ register "PcieRpLtrEnable[6]" = "1" ++ end ++ ++ # M.2 WWAN - x2 ++ device ref pcie_rp5 on ++ register "PcieRpEnable[4]" = "1" ++ register "PcieRpClkReqSupport[4]" = "1" ++ register "PcieRpClkReqNumber[4]" = "3" ++ register "PcieRpClkSrcNumber[4]" = "3" ++ register "PcieRpAdvancedErrorReporting[4]" = "1" ++ register "PcieRpLtrEnable[4]" = "1" ++ end ++ ++ # TB3 (Alpine Ridge LP) - x2 ++ device ref pcie_rp9 on ++ register "PcieRpEnable[8]" = "1" ++ register "PcieRpClkReqSupport[8]" = "1" ++ register "PcieRpClkReqNumber[8]" = "4" ++ register "PcieRpClkSrcNumber[8]" = "4" ++ register "PcieRpAdvancedErrorReporting[8]" = "1" ++ register "PcieRpLtrEnable[8]" = "1" ++ register "PcieRpHotPlug[8]" = "1" ++ end ++ ++ # M.2 2280 caddy - x2 ++ device ref pcie_rp11 on ++ register "PcieRpEnable[10]" = "1" ++ register "PcieRpClkReqSupport[10]" = "1" ++ register "PcieRpClkReqNumber[10]" = "5" ++ register "PcieRpClkSrcNumber[10]" = "5" ++ register "PcieRpAdvancedErrorReporting[10]" = "1" ++ register "PcieRpLtrEnable[10]" = "1" ++ end ++ end ++end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt +new file mode 100644 +index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840 +GIT binary patch +literal 4106 +zcmeHJUu+a*5TCu>yW9JAmoD2P9tqx`iFWXCLD09RaS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU +zTXkLEL3ly5L&oUX#CS7?b2%Kad?s-#@;mhg8>>>#S&)d2I +zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP +zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS +z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp +zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw +z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b +znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U +z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6 +zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z +XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads +new file mode 100644 +index 0000000000..fcfbd75a92 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads +@@ -0,0 +1,19 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ (eDP, ++ DP1, ++ DP2, ++ HDMI1, ++ HDMI2, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c +new file mode 100644 +index 0000000000..a98dd2bc4e +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c +@@ -0,0 +1,199 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include "../../gpio.h" ++ ++static const struct pad_config gpio_table[] = { ++ /* ------- GPIO Community 0 ------- */ ++ ++ /* ------- GPIO Group GPP_A ------- */ ++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ ++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ ++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ ++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ ++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ ++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ ++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ ++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ ++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ ++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ ++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ ++ PAD_NC(GPP_A11, NONE), ++ PAD_NC(GPP_A12, NONE), ++ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */ ++ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */ ++ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */ ++ PAD_NC(GPP_A16, NONE), ++ PAD_NC(GPP_A17, NONE), ++ PAD_NC(GPP_A18, NONE), ++ PAD_NC(GPP_A19, NONE), ++ PAD_NC(GPP_A20, NONE), ++ PAD_NC(GPP_A21, NONE), ++ PAD_NC(GPP_A22, NONE), ++ PAD_NC(GPP_A23, NONE), ++ ++ /* ------- GPIO Group GPP_B ------- */ ++ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), ++ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), ++ PAD_NC(GPP_B2, NONE), ++ PAD_NC(GPP_B3, NONE), ++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */ ++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */ ++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */ ++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */ ++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */ ++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */ ++ PAD_NC(GPP_B11, NONE), ++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ ++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ ++ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */ ++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ ++ PAD_NC(GPP_B16, NONE), ++ PAD_NC(GPP_B17, NONE), ++ PAD_NC(GPP_B18, NONE), ++ PAD_NC(GPP_B19, NONE), ++ PAD_NC(GPP_B20, NONE), ++ PAD_NC(GPP_B21, NONE), ++ PAD_NC(GPP_B22, NONE), ++ PAD_NC(GPP_B23, NONE), ++ ++ /* ------- GPIO Community 1 ------- */ ++ ++ /* ------- GPIO Group GPP_C ------- */ ++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ ++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ ++ PAD_CFG_GPO(GPP_C2, 1, DEEP), ++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ ++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ ++ PAD_NC(GPP_C5, NONE), ++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ ++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ ++ PAD_NC(GPP_C8, NONE), ++ PAD_NC(GPP_C9, NONE), ++ PAD_NC(GPP_C10, NONE), ++ PAD_NC(GPP_C11, NONE), ++ PAD_NC(GPP_C12, NONE), ++ PAD_NC(GPP_C13, NONE), ++ PAD_NC(GPP_C14, NONE), ++ PAD_NC(GPP_C15, NONE), ++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ ++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ ++ PAD_NC(GPP_C18, NONE), ++ PAD_NC(GPP_C19, NONE), ++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */ ++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ ++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ ++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ ++ ++ /* ------- GPIO Group GPP_D ------- */ ++ PAD_NC(GPP_D0, NONE), ++ PAD_NC(GPP_D1, NONE), ++ PAD_NC(GPP_D2, NONE), ++ PAD_NC(GPP_D3, NONE), ++ PAD_NC(GPP_D4, NONE), ++ PAD_NC(GPP_D5, NONE), ++ PAD_NC(GPP_D6, NONE), ++ PAD_NC(GPP_D7, NONE), ++ PAD_NC(GPP_D8, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */ ++ PAD_NC(GPP_D10, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */ ++ PAD_NC(GPP_D13, NONE), ++ PAD_NC(GPP_D14, NONE), ++ PAD_NC(GPP_D15, NONE), ++ PAD_NC(GPP_D16, NONE), ++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ ++ PAD_NC(GPP_D18, NONE), ++ PAD_NC(GPP_D19, NONE), ++ PAD_NC(GPP_D20, NONE), ++ PAD_NC(GPP_D21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ ++ PAD_NC(GPP_D23, NONE), ++ ++ /* ------- GPIO Group GPP_E ------- */ ++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ ++ PAD_NC(GPP_E1, NONE), ++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ ++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ ++ PAD_NC(GPP_E5, NONE), ++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */ ++ PAD_NC(GPP_E7, NONE), ++ PAD_NC(GPP_E8, NONE), ++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ ++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ ++ PAD_NC(GPP_E11, NONE), ++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ ++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ ++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ ++ PAD_NC(GPP_E15, NONE), ++ PAD_NC(GPP_E16, NONE), ++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ ++ PAD_NC(GPP_E18, NONE), ++ PAD_CFG_GPO(GPP_E19, 0, DEEP), ++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ ++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ ++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */ ++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */ ++ ++ /* ------- GPIO Community 2 ------- */ ++ ++ /* -------- GPIO Group GPD -------- */ ++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ ++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ ++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ ++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ ++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ ++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ ++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ ++ PAD_NC(GPD7, NONE), ++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ ++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ ++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ ++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ ++ ++ /* ------- GPIO Community 3 ------- */ ++ ++ /* ------- GPIO Group GPP_F ------- */ ++ PAD_CFG_GPO(GPP_F0, 0, DEEP), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */ ++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */ ++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ ++ PAD_NC(GPP_F5, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ ++ PAD_NC(GPP_F21, NONE), ++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */ ++ ++ /* ------- GPIO Group GPP_G ------- */ ++ PAD_NC(GPP_G0, NONE), ++ PAD_NC(GPP_G1, NONE), ++ PAD_NC(GPP_G2, NONE), ++ PAD_NC(GPP_G3, NONE), ++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ ++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ ++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ ++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ ++}; ++ ++void variant_config_gpios(void) ++{ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c +new file mode 100644 +index 0000000000..b1d96c5a76 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c +@@ -0,0 +1,90 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257 ++ 0x17aa2258, // Subsystem ID ++ 11, ++ AZALIA_SUBVENDOR(0, 0x17aa2258), ++ ++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_MIC_IN, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 2, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( ++ AZALIA_INTEGRATED, ++ AZALIA_INTERNAL, ++ AZALIA_SPEAKER, ++ AZALIA_OTHER_ANALOG, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_NO_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_MIC_IN, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 3, 0 ++ )), ++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device ++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), ++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, ++ AZALIA_HP_OUT, ++ AZALIA_STEREO_MONO_1_8, ++ AZALIA_BLACK, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 15 ++ )), ++ ++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI ++ 0x80860101, // Subsystem ID ++ 4, ++ AZALIA_SUBVENDOR(2, 0x80860101), ++ ++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( ++ AZALIA_JACK, ++ AZALIA_DIGITAL_DISPLAY, ++ AZALIA_DIGITAL_OTHER_OUT, ++ AZALIA_OTHER_DIGITAL, ++ AZALIA_COLOR_UNKNOWN, ++ AZALIA_JACK_PRESENCE_DETECT, ++ 1, 0 ++ )), ++}; ++ ++const u32 pc_beep_verbs[] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +new file mode 100644 +index 0000000000..001e934b3a +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +@@ -0,0 +1,44 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const struct pad_config memory_id_gpio_table[] = { ++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ ++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ ++}; ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ int spd_idx; ++ char spd_name[20]; ++ size_t spd_size; ++ ++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; ++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */ ++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ ++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; ++ ++ /* Get SPD for soldered RAM SPD (CH A) */ ++ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); ++ ++ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | ++ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; ++ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); ++ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx); ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size); ++ ++ /* Get SPD for memory slot (CH B) */ ++ struct spd_block blk = { .addr_map = { [1] = 0x51, } }; ++ get_spd_smbus(&blk); ++ dump_spd_info(&blk); ++ ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; ++} +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +new file mode 100644 +index 0000000000..d4afca20c4 +--- /dev/null ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb +@@ -0,0 +1,103 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++chip soc/intel/skylake ++ device domain 0 on ++ device ref south_xhci on ++ register "usb2_ports" = "{ ++ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) ++ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) ++ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) ++ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C) ++ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera) ++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) ++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) ++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) ++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) ++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) ++ }" ++ register "usb3_ports" = "{ ++ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) ++ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) ++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) ++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C) ++ }" ++ end ++ ++ device ref sata on ++ # SATA_2 - Main M.2 SATA SSD ++ register "SataPortsEnable[2]" = "1" ++ register "SataPortsDevSlp[2]" = "1" ++ end ++ ++ # PCIe controller 1 - 1x2+2x1 ++ # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0 ++ # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1 ++ # ++ # PCIe controller 2 - 2x1+1x2 (lane reversal) ++ # PCIE 5 - GBE - GBE - CLKOUT2 - CLKREQ2 (clobbers RP8) ++ # PCIE 6 - RP7 - WLAN - CLKOUT3 - CLKREQ3 ++ # PCIE 7-8 - RP5 - TB3 - CLKOUT4 - CLKREQ4 ++ # ++ # PCIe controller 3 - 1x4 (lane reversal) ++ # PCIE 9-12 - RP9 - SSD - CLKOUT5 - CLKREQ5 ++ ++ # dGPU - x2 ++ device ref pcie_rp1 on ++ register "PcieRpEnable[0]" = "1" ++ register "PcieRpClkReqSupport[0]" = "1" ++ register "PcieRpClkReqNumber[0]" = "0" ++ register "PcieRpClkSrcNumber[0]" = "0" ++ register "PcieRpAdvancedErrorReporting[0]" = "1" ++ register "PcieRpLtrEnable[0]" = "1" ++ end ++ ++ # M.2 WWAN - x1 ++ device ref pcie_rp4 on ++ register "PcieRpEnable[3]" = "1" ++ register "PcieRpClkReqSupport[3]" = "1" ++ register "PcieRpClkReqNumber[3]" = "1" ++ register "PcieRpClkSrcNumber[3]" = "1" ++ register "PcieRpAdvancedErrorReporting[3]" = "1" ++ register "PcieRpLtrEnable[3]" = "1" ++ end ++ ++ # Ethernet (clobbers RP8) ++ device ref gbe on ++ register "LanClkReqSupported" = "1" ++ register "LanClkReqNumber" = "2" ++ register "EnableLanLtr" = "1" ++ register "EnableLanK1Off" = "1" ++ end ++ ++ # M.2 WLAN - x1 ++ device ref pcie_rp7 on ++ register "PcieRpEnable[6]" = "1" ++ register "PcieRpClkReqSupport[6]" = "1" ++ register "PcieRpClkReqNumber[6]" = "3" ++ register "PcieRpClkSrcNumber[6]" = "3" ++ register "PcieRpAdvancedErrorReporting[6]" = "1" ++ register "PcieRpLtrEnable[6]" = "1" ++ end ++ ++ # TB3 (Alpine Ridge LP) - x2 ++ device ref pcie_rp5 on ++ register "PcieRpEnable[4]" = "1" ++ register "PcieRpClkReqSupport[4]" = "1" ++ register "PcieRpClkReqNumber[4]" = "4" ++ register "PcieRpClkSrcNumber[4]" = "4" ++ register "PcieRpAdvancedErrorReporting[4]" = "1" ++ register "PcieRpLtrEnable[4]" = "1" ++ register "PcieRpHotPlug[4]" = "1" ++ end ++ ++ # M.2 2280 SSD - x2 ++ device ref pcie_rp9 on ++ register "PcieRpEnable[8]" = "1" ++ register "PcieRpClkReqSupport[8]" = "1" ++ register "PcieRpClkReqNumber[8]" = "5" ++ register "PcieRpClkSrcNumber[8]" = "5" ++ register "PcieRpAdvancedErrorReporting[8]" = "1" ++ register "PcieRpLtrEnable[8]" = "1" ++ end ++ end ++end +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin +new file mode 100644 +index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e +GIT binary patch +literal 512 +zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1t+8`-(puhlu3{YAD +YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($ + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin 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exploiting CVE-2017-5705. +# See https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html + +# xx80-*-maximized boards require of you initially call one of the +# following to have gbe.bin ifd.bin and me.bin +# - blobs/xx80/download_clean_me_and_deguard.sh +# To download Lenovo original ME binary, neuter+deactivate ME, produce +# reduced IFD ME region and expanded BIOS IFD region. +# - blobs/xx80/extract_and_deguard.sh +# To extract ME binary, GBE and IFD blobs and apply the deguard exploit to the the ME binary. + +# Make the Coreboot build depend on the following 3rd party blobs: +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ + $(pwd)/blobs/xx80/me.bin + +$(pwd)/blobs/kabylake/Fsp_M.fd: + COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ + $(pwd)/blobs/kabylake/fetch_split_fsp.sh $(pwd)/blobs/kabylake + +$(pwd)/blobs/kabylake/Fsp_S.fd: + COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ + $(pwd)/blobs/kabylake/fetch_split_fsp.sh $(pwd)/blobs/kabylake + +$(pwd)/blobs/xx80/me.bin: + COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ + $(pwd)/blobs/xx80/download_clean_deguard_me.sh $(pwd)/blobs/xx80 \ No newline at end of file