mirror of
https://github.com/linuxboot/heads.git
synced 2025-04-07 19:34:26 +00:00
dasharo coreboot fork patches: rename 501 and add PR0 patch; add coreboot config bits
Signed-off-by: Thierry Laurion <insurgo@riseup.net>
This commit is contained in:
Thierry Laurion
parent
515ca5db95
commit
a5c1d8e929
@ -428,6 +428,7 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
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CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
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CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
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CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
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# CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM is not set
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CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
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CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
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CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
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@ -489,8 +490,10 @@ CONFIG_PCIEXP_HOTPLUG=y
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CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
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CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
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CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
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CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
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# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
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# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set
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CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
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CONFIG_RCBA_LENGTH=0x4000
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@ -730,9 +733,11 @@ CONFIG_INTEL_TXT_LIB=y
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# CONFIG_INTEL_TXT is not set
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# CONFIG_STM is not set
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# CONFIG_INTEL_CBNT_SUPPORT is not set
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CONFIG_BOOTMEDIA_LOCK_NONE=y
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# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
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# CONFIG_BOOTMEDIA_LOCK_NONE is not set
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CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
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# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
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CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y
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# CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set
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# CONFIG_BOOTMEDIA_SMM_BWP is not set
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# end of Security
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@ -0,0 +1,391 @@
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From ff22122c229bbe2109de92ded773493428f7ece9 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
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Date: Sun, 20 Oct 2024 13:15:19 +0200
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Subject: [PATCH] soc/intel/lockdown: Allow locking down SPI and LPC in SMM
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Heads payload uses APM_CNT_FINALIZE SMI to set and lock down
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the SPI controller with PR0 flash protection. Add new option
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to skip LPC and FAST SPI lock down in coreboot and move it
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to APM_CNT_FINALIZE SMI handler.
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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---
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src/soc/intel/alderlake/finalize.c | 4 ++-
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src/soc/intel/cannonlake/finalize.c | 3 +-
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src/soc/intel/common/block/lpc/Makefile.inc | 4 +++
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src/soc/intel/common/block/smm/smihandler.c | 10 ++++++
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.../common/pch/include/intelpch/lockdown.h | 3 ++
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src/soc/intel/common/pch/lockdown/Kconfig | 15 ++++++++
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.../intel/common/pch/lockdown/Makefile.inc | 5 +++
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src/soc/intel/common/pch/lockdown/lockdown.c | 33 +++++------------
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.../intel/common/pch/lockdown/lockdown_lpc.c | 23 ++++++++++++
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.../intel/common/pch/lockdown/lockdown_spi.c | 35 +++++++++++++++++++
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src/soc/intel/denverton_ns/lpc.c | 3 +-
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src/soc/intel/elkhartlake/finalize.c | 3 +-
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src/soc/intel/jasperlake/finalize.c | 3 +-
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src/soc/intel/meteorlake/finalize.c | 3 +-
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src/soc/intel/skylake/finalize.c | 3 +-
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src/soc/intel/tigerlake/finalize.c | 3 +-
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src/soc/intel/xeon_sp/finalize.c | 3 +-
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17 files changed, 123 insertions(+), 33 deletions(-)
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create mode 100644 src/soc/intel/common/pch/lockdown/lockdown_lpc.c
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create mode 100644 src/soc/intel/common/pch/lockdown/lockdown_spi.c
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diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
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index 460c8af174e..9cd9351d96a 100644
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--- a/src/soc/intel/alderlake/finalize.c
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+++ b/src/soc/intel/alderlake/finalize.c
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@@ -84,7 +84,9 @@ static void soc_finalize(void *unused)
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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- apm_control(APM_CNT_FINALIZE);
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+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
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+ apm_control(APM_CNT_FINALIZE);
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+
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tbt_finalize();
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if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
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CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
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diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
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index ba7fc69b552..b5f727e97c7 100644
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--- a/src/soc/intel/cannonlake/finalize.c
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+++ b/src/soc/intel/cannonlake/finalize.c
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@@ -87,7 +87,8 @@ static void soc_finalize(void *unused)
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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- apm_control(APM_CNT_FINALIZE);
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+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
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+ apm_control(APM_CNT_FINALIZE);
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if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
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CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
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heci1_disable();
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diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc
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index b510cd0ec35..60792654b5a 100644
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--- a/src/soc/intel/common/block/lpc/Makefile.inc
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+++ b/src/soc/intel/common/block/lpc/Makefile.inc
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@@ -5,3 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c
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+
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+ifeq ($(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM),y)
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+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
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+endif
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diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
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index 4bfd17bfd07..dcd74764957 100644
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--- a/src/soc/intel/common/block/smm/smihandler.c
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+++ b/src/soc/intel/common/block/smm/smihandler.c
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@@ -15,12 +15,14 @@
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <elog.h>
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+#include <intelblocks/cfg.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/oc_wdt.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/smihandler.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/uart.h>
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+#include <intelpch/lockdown.h>
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#include <smmstore.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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@@ -343,6 +345,14 @@ static void finalize(void)
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}
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finalize_done = 1;
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+ if (CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) {
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+ /* SPI lock down configuration */
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+ fast_spi_lockdown_bios(CHIPSET_LOCKDOWN_COREBOOT);
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+
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+ /* LPC/eSPI lock down configuration */
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+ lpc_lockdown_config(CHIPSET_LOCKDOWN_COREBOOT);
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+ }
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+
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if (CONFIG(SPI_FLASH_SMM))
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/* Re-init SPI driver to handle locked BAR */
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fast_spi_init();
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diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h
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index b5aba06fe0e..1b96f41a2a4 100644
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--- a/src/soc/intel/common/pch/include/intelpch/lockdown.h
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+++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h
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@@ -22,4 +22,7 @@ int get_lockdown_config(void);
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*/
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void soc_lockdown_config(int chipset_lockdown);
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+void fast_spi_lockdown_bios(int chipset_lockdown);
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+void lpc_lockdown_config(int chipset_lockdown);
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+
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#endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */
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diff --git a/src/soc/intel/common/pch/lockdown/Kconfig b/src/soc/intel/common/pch/lockdown/Kconfig
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index 8fce5e785c2..fbeb341e9ac 100644
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--- a/src/soc/intel/common/pch/lockdown/Kconfig
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+++ b/src/soc/intel/common/pch/lockdown/Kconfig
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@@ -1,7 +1,22 @@
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config SOC_INTEL_COMMON_PCH_LOCKDOWN
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bool
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default n
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+ select HAVE_INTEL_CHIPSET_LOCKDOWN
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help
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This option allows to have chipset lockdown for DMI, FAST_SPI and
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soc_lockdown_config() to implement any additional lockdown as PMC,
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LPC for supported PCH.
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+
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+config SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM
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+ bool "Lock down SPI controller in SMM"
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+ default n
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+ depends on HAVE_SMI_HANDLER
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+ select SPI_FLASH_SMM
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+ help
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+ This option allows to have chipset lockdown for FAST_SPI and LPC for
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+ supported PCH. If selected, coreboot will skip locking down the SPI
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+ and LPC controller. The payload or OS is responsible for locking it
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+ using APM_CNT_FINALIZE SMI. Used by heads to set and lock PR0 flash
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+ protection.
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+
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+ If unsure, say N.
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\ No newline at end of file
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diff --git a/src/soc/intel/common/pch/lockdown/Makefile.inc b/src/soc/intel/common/pch/lockdown/Makefile.inc
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index 71466f8edd1..64aad562acf 100644
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--- a/src/soc/intel/common/pch/lockdown/Makefile.inc
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+++ b/src/soc/intel/common/pch/lockdown/Makefile.inc
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@@ -1,2 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-only
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ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown.c
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+ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_lpc.c
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+ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_spi.c
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+
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+smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_lpc.c
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+smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_spi.c
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diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
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index 1b1d99cc0c9..7e52fb826fe 100644
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--- a/src/soc/intel/common/pch/lockdown/lockdown.c
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+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
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@@ -61,21 +61,24 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
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/* Set FAST_SPI opcode menu */
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fast_spi_set_opcode_menu();
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- /* Discrete Lock Flash PR registers */
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- fast_spi_pr_dlock();
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-
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/* Check if SPI transaction is pending */
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fast_spi_cycle_in_progress();
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/* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */
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fast_spi_clear_outstanding_status();
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- /* Lock FAST_SPIBAR */
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- fast_spi_lock_bar();
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-
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/* Set Vendor Component Lock (VCL) */
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fast_spi_vscc0_lock();
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+ if (CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM))
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+ return;
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+
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+ /* Discrete Lock Flash PR registers */
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+ fast_spi_pr_dlock();
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+
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+ /* Lock FAST_SPIBAR */
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+ fast_spi_lock_bar();
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+
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/* Set BIOS Interface Lock, BIOS Lock */
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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/* BIOS Interface Lock */
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@@ -95,24 +98,6 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
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}
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}
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-static void lpc_lockdown_config(int chipset_lockdown)
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-{
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- /* Set BIOS Interface Lock, BIOS Lock */
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- if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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- /* BIOS Interface Lock */
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- lpc_set_bios_interface_lock_down();
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-
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- /* Only allow writes in SMM */
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- if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) {
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- lpc_set_eiss();
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- lpc_enable_wp();
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- }
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-
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- /* BIOS Lock */
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- lpc_set_lock_enable();
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- }
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-}
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-
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static void sa_lockdown_config(int chipset_lockdown)
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{
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if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SA))
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diff --git a/src/soc/intel/common/pch/lockdown/lockdown_lpc.c b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c
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new file mode 100644
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index 00000000000..69278ea343f
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--- /dev/null
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+++ b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c
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@@ -0,0 +1,23 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <intelblocks/cfg.h>
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+#include <intelblocks/lpc_lib.h>
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+#include <intelpch/lockdown.h>
|
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+
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+void lpc_lockdown_config(int chipset_lockdown)
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+{
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+ /* Set BIOS Interface Lock, BIOS Lock */
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+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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+ /* BIOS Interface Lock */
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+ lpc_set_bios_interface_lock_down();
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+
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+ /* Only allow writes in SMM */
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+ if (CONFIG(BOOTMEDIA_SMM_BWP)) {
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+ lpc_set_eiss();
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+ lpc_enable_wp();
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+ }
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+
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+ /* BIOS Lock */
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+ lpc_set_lock_enable();
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+ }
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+}
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diff --git a/src/soc/intel/common/pch/lockdown/lockdown_spi.c b/src/soc/intel/common/pch/lockdown/lockdown_spi.c
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new file mode 100644
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index 00000000000..fa09cec7c2e
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--- /dev/null
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+++ b/src/soc/intel/common/pch/lockdown/lockdown_spi.c
|
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@@ -0,0 +1,35 @@
|
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
|
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+#include <intelblocks/cfg.h>
|
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+#include <intelblocks/fast_spi.h>
|
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+#include <intelpch/lockdown.h>
|
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+
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+void fast_spi_lockdown_bios(int chipset_lockdown)
|
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+{
|
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+ if (!CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI))
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+ return;
|
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+
|
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+ /* Discrete Lock Flash PR registers */
|
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+ fast_spi_pr_dlock();
|
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+
|
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+ /* Lock FAST_SPIBAR */
|
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+ fast_spi_lock_bar();
|
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+
|
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+ /* Set BIOS Interface Lock, BIOS Lock */
|
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+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
|
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+ /* BIOS Interface Lock */
|
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+ fast_spi_set_bios_interface_lock_down();
|
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+
|
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+ /* Only allow writes in SMM */
|
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+ if (CONFIG(BOOTMEDIA_SMM_BWP)) {
|
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+ fast_spi_set_eiss();
|
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+ fast_spi_enable_wp();
|
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+ }
|
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+
|
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+ /* BIOS Lock */
|
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+ fast_spi_set_lock_enable();
|
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+
|
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+ /* EXT BIOS Lock */
|
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+ fast_spi_set_ext_bios_lock_enable();
|
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+ }
|
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+}
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diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
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index 7ebca1eb946..8d8acf05088 100644
|
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--- a/src/soc/intel/denverton_ns/lpc.c
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+++ b/src/soc/intel/denverton_ns/lpc.c
|
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@@ -536,7 +536,8 @@ static const struct pci_driver lpc_driver __pci_driver = {
|
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static void finalize_chipset(void *unused)
|
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{
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- apm_control(APM_CNT_FINALIZE);
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+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
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+ apm_control(APM_CNT_FINALIZE);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
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diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
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index 275413b4efa..802d02cb596 100644
|
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--- a/src/soc/intel/elkhartlake/finalize.c
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+++ b/src/soc/intel/elkhartlake/finalize.c
|
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@@ -43,7 +43,8 @@ static void soc_finalize(void *unused)
|
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
|
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|
||||
pch_finalize();
|
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- apm_control(APM_CNT_FINALIZE);
|
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+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
|
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+ apm_control(APM_CNT_FINALIZE);
|
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if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
|
||||
CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
|
||||
heci_finalize();
|
||||
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
|
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index 6cff7a80f30..1b68cc51786 100644
|
||||
--- a/src/soc/intel/jasperlake/finalize.c
|
||||
+++ b/src/soc/intel/jasperlake/finalize.c
|
||||
@@ -75,7 +75,8 @@ static void soc_finalize(void *unused)
|
||||
printk(BIOS_DEBUG, "Finalizing chipset.\n");
|
||||
|
||||
pch_finalize();
|
||||
- apm_control(APM_CNT_FINALIZE);
|
||||
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
|
||||
+ apm_control(APM_CNT_FINALIZE);
|
||||
|
||||
/* Indicate finalize step with post code */
|
||||
post_code(POSTCODE_OS_BOOT);
|
||||
diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c
|
||||
index a977b0516e5..951153fa812 100644
|
||||
--- a/src/soc/intel/meteorlake/finalize.c
|
||||
+++ b/src/soc/intel/meteorlake/finalize.c
|
||||
@@ -75,7 +75,8 @@ static void soc_finalize(void *unused)
|
||||
printk(BIOS_DEBUG, "Finalizing chipset.\n");
|
||||
|
||||
pch_finalize();
|
||||
- apm_control(APM_CNT_FINALIZE);
|
||||
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
|
||||
+ apm_control(APM_CNT_FINALIZE);
|
||||
tbt_finalize();
|
||||
sa_finalize();
|
||||
if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
|
||||
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
|
||||
index fd80aeac1a0..a147b62e46f 100644
|
||||
--- a/src/soc/intel/skylake/finalize.c
|
||||
+++ b/src/soc/intel/skylake/finalize.c
|
||||
@@ -106,7 +106,8 @@ static void soc_finalize(void *unused)
|
||||
pch_finalize_script(dev);
|
||||
|
||||
soc_lockdown(dev);
|
||||
- apm_control(APM_CNT_FINALIZE);
|
||||
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
|
||||
+ apm_control(APM_CNT_FINALIZE);
|
||||
|
||||
/* Indicate finalize step with post code */
|
||||
post_code(POSTCODE_OS_BOOT);
|
||||
diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c
|
||||
index cd02745a9e6..06ce243fe72 100644
|
||||
--- a/src/soc/intel/tigerlake/finalize.c
|
||||
+++ b/src/soc/intel/tigerlake/finalize.c
|
||||
@@ -55,7 +55,8 @@ static void soc_finalize(void *unused)
|
||||
printk(BIOS_DEBUG, "Finalizing chipset.\n");
|
||||
|
||||
pch_finalize();
|
||||
- apm_control(APM_CNT_FINALIZE);
|
||||
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
|
||||
+ apm_control(APM_CNT_FINALIZE);
|
||||
tbt_finalize();
|
||||
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
|
||||
heci1_disable();
|
||||
diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c
|
||||
index af630fe8127..8e409b8c439 100644
|
||||
--- a/src/soc/intel/xeon_sp/finalize.c
|
||||
+++ b/src/soc/intel/xeon_sp/finalize.c
|
||||
@@ -59,7 +59,8 @@ static void soc_finalize(void *unused)
|
||||
if (!CONFIG(USE_PM_ACPI_TIMER))
|
||||
setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
|
||||
|
||||
- apm_control(APM_CNT_FINALIZE);
|
||||
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
|
||||
+ apm_control(APM_CNT_FINALIZE);
|
||||
lock_pam0123();
|
||||
|
||||
if (CONFIG_MAX_SOCKET > 1) {
|
||||
Loading…
x
Reference in New Issue
Block a user