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Revert "t440p/w541 use broadwell mrc blob"
This reverts commit 95322c66291d7e34c437f77f12cdd89707a6b0ce. Signed-off-by: gaspar-ilom <gasparilom@riseup.net>
This commit is contained in:
gaspar-ilom
parent
95322c6629
commit
9227476afa
1
blobs/broadwell/.gitignore
vendored
1
blobs/broadwell/.gitignore
vendored
@ -1 +0,0 @@
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mrc.bin
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@ -1,44 +0,0 @@
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#!/usr/bin/env bash
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set -e
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function usage() {
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echo -n \
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"Usage: $(basename "$0") path_to_output_directory
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Obtain mrc.bin from a Broadwell Chromebook firmware image.
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"
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}
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MRC_BIN_HASH="dd05ab481e1fe0ce20ade164cf3dbef3c479592801470e6e79faa17624751343"
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if [[ "${BASH_SOURCE[0]}" == "$0" ]]; then
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if [[ "${1:-}" == "--help" ]]; then
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usage
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else
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if [[ -z "${COREBOOT_DIR}" ]]; then
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echo "ERROR: No COREBOOT_DIR variable defined."
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exit 1
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fi
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output_dir="$(realpath "${1:-./}")"
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# Obtain broadwell mrc blob
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if [[ ! -f "${output_dir}/mrc.bin" ]]; then
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pushd "${COREBOOT_DIR}"
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make -C util/cbfstool
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cd util/chromeos
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./crosfirmware.sh samus
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../cbfstool/cbfstool coreboot-*.bin extract -f mrc.bin -n mrc.bin -r RO_SECTION
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mv mrc.bin "${output_dir}/mrc.bin"
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popd
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fi
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if ! echo "${MRC_BIN_HASH} ${output_dir}/mrc.bin" | sha256sum --check; then
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echo "ERROR: SHA256 checksum for mrc.bin doesn't match."
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exit 1
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fi
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fi
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fi
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@ -49,11 +49,7 @@ export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal"
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# Make the Coreboot build depend on the following 3rd party blobs:
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$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \
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$(pwd)/blobs/broadwell/mrc.bin $(pwd)/blobs/t440p/me.bin
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$(pwd)/blobs/broadwell/mrc.bin:
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COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \
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$(pwd)/blobs/broadwell/obtain-mrc $(pwd)/blobs/broadwell
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$(pwd)/blobs/t440p/me.bin
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$(pwd)/blobs/t440p/me.bin:
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COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \
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@ -49,11 +49,7 @@ export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal"
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# Make the Coreboot build depend on the following 3rd party blobs:
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$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \
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$(pwd)/blobs/broadwell/mrc.bin $(pwd)/blobs/w541/me.bin
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$(pwd)/blobs/broadwell/mrc.bin:
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COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \
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$(pwd)/blobs/broadwell/obtain-mrc $(pwd)/blobs/broadwell
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$(pwd)/blobs/w541/me.bin
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$(pwd)/blobs/w541/me.bin:
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COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \
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@ -153,9 +153,9 @@ CONFIG_MAX_SOCKET=1
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CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
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CONFIG_TPM_PIRQ=0x0
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CONFIG_DCACHE_RAM_BASE=0xff7c0000
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CONFIG_DCACHE_RAM_SIZE=0x10000
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CONFIG_DCACHE_RAM_SIZE=0x40000
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CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
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CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
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CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
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CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
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CONFIG_HAVE_INTEL_FIRMWARE=y
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CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
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@ -275,7 +275,7 @@ CONFIG_SMM_MODULE_STACK_SIZE=0x400
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CONFIG_SERIRQ_CONTINUOUS_MODE=y
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CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
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CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
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CONFIG_EHCI_BAR=0xd8000000
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CONFIG_EHCI_BAR=0xe8000000
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CONFIG_ACPI_CPU_STRING="CP%02X"
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CONFIG_STACK_SIZE=0x2000
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CONFIG_IED_REGION_SIZE=0x400000
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@ -284,9 +284,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
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CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
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CONFIG_INTEL_GMA_BCLM_WIDTH=16
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CONFIG_BOOTBLOCK_IN_CBFS=y
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CONFIG_HAVE_MRC=y
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CONFIG_MRC_FILE="@BLOB_DIR@/broadwell/mrc.bin"
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CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
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CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
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CONFIG_HPET_MIN_TICKS=0x80
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CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
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CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
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@ -337,9 +335,7 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
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# Northbridge
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#
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CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
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# CONFIG_USE_NATIVE_RAMINIT is not set
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CONFIG_USE_BROADWELL_MRC=y
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CONFIG_HASWELL_HIDE_PEG_FROM_MRC=y
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CONFIG_USE_NATIVE_RAMINIT=y
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#
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# Southbridge
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@ -695,6 +691,8 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
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# General Debug Settings
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#
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# CONFIG_DEBUG_CBFS is not set
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CONFIG_HAVE_DEBUG_RAM_SETUP=y
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# CONFIG_DEBUG_RAM_SETUP is not set
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CONFIG_HAVE_DEBUG_SMBUS=y
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# CONFIG_DEBUG_SMBUS is not set
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# CONFIG_DEBUG_CONSOLE_INIT is not set
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@ -153,9 +153,9 @@ CONFIG_MAX_SOCKET=1
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CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
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CONFIG_TPM_PIRQ=0x0
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CONFIG_DCACHE_RAM_BASE=0xff7c0000
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CONFIG_DCACHE_RAM_SIZE=0x10000
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CONFIG_DCACHE_RAM_SIZE=0x40000
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CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
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CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
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CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
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CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
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CONFIG_HAVE_INTEL_FIRMWARE=y
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CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
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@ -275,7 +275,7 @@ CONFIG_SMM_MODULE_STACK_SIZE=0x400
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CONFIG_SERIRQ_CONTINUOUS_MODE=y
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CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
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CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
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CONFIG_EHCI_BAR=0xd8000000
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CONFIG_EHCI_BAR=0xe8000000
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CONFIG_ACPI_CPU_STRING="CP%02X"
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CONFIG_STACK_SIZE=0x2000
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CONFIG_IED_REGION_SIZE=0x400000
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@ -284,9 +284,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
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CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
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CONFIG_INTEL_GMA_BCLM_WIDTH=16
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CONFIG_BOOTBLOCK_IN_CBFS=y
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CONFIG_HAVE_MRC=y
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CONFIG_MRC_FILE="@BLOB_DIR@/broadwell/mrc.bin"
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CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
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CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
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CONFIG_HPET_MIN_TICKS=0x80
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CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
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CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
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@ -337,9 +335,7 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
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# Northbridge
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#
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CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
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# CONFIG_USE_NATIVE_RAMINIT is not set
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CONFIG_USE_BROADWELL_MRC=y
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CONFIG_HASWELL_HIDE_PEG_FROM_MRC=y
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CONFIG_USE_NATIVE_RAMINIT=y
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#
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# Southbridge
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@ -694,6 +690,8 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
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# General Debug Settings
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#
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# CONFIG_DEBUG_CBFS is not set
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CONFIG_HAVE_DEBUG_RAM_SETUP=y
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# CONFIG_DEBUG_RAM_SETUP is not set
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CONFIG_HAVE_DEBUG_SMBUS=y
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# CONFIG_DEBUG_SMBUS is not set
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# CONFIG_DEBUG_CONSOLE_INIT is not set
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