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supermicro-x11ssh: update patch to c933f4972abb7
This commit is contained in:
Trammell hudson
parent
97c4e7b02e
commit
8ff038f0c7
@ -1,4 +1,4 @@
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From 2d795267e2fe78af4eb4070e2562aed5fec25dde Mon Sep 17 00:00:00 2001
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From c933f4972abb7acca4981d193cfddd9d4290f3ff Mon Sep 17 00:00:00 2001
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From: Christian Walter <christian.walter@9elements.com>
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Date: Fri, 10 May 2019 15:52:00 +0200
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Subject: [PATCH] mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
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@ -9,7 +9,7 @@ Working:
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* SeaBios payload
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* LinuxBoot payload
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* IPMI of BMC
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* PCIe, SATA, USB ports
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* PCIe, SATA, USB and M.2 ports
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* RS232 serial
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* Native graphics init
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@ -44,10 +44,10 @@ index 0f3105f..08689b7 100644
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diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11ssh-tf.md
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new file mode 100644
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index 0000000..e23309d
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index 0000000..b35874d
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--- /dev/null
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+++ b/Documentation/mainboard/supermicro/x11ssh-tf.md
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@@ -0,0 +1,73 @@
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@@ -0,0 +1,74 @@
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+# Supermicro X11SSH-TF
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+
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+This section details how to run coreboot on the [Supermicro X11SSH-TF].
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@ -76,13 +76,14 @@ index 0000000..e23309d
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+## Known issues
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+
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+- Intel SGX causes secondary APs to crash (disabled for now).
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+- MP init causes secondary APs to crash (fix in gerrit).
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+- Tianocore doesn't work with Aspeed NGI, as it's text mode only.
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+- The IPMI driver times out on cold boot (fix in gerrit).
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+- After S5 resume coreboot detects more DIMMs than installed, causing FSP-M
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+ to fail.
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+
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+## Working
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+## Tested and working
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+
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+- USB
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+- USB ports
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+- M.2 2280 NVMe slot
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+- 2x 10GB Ethernet
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+- SATA
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+- RS232
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@ -841,10 +842,10 @@ index 0000000..f3eb3ef
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+Flashrom support: y
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diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
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new file mode 100644
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index 0000000..dbb589f
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index 0000000..38699ee
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--- /dev/null
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+++ b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
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@@ -0,0 +1,290 @@
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@@ -0,0 +1,289 @@
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+chip soc/intel/skylake
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+
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+ # Enable deep Sx states
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@ -860,9 +861,10 @@ index 0000000..dbb589f
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+ register "gpe0_dw1" = "GPP_D"
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+ register "gpe0_dw2" = "GPP_E"
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+
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+ register "gen1_dec" = "0x007c0a01" # Super IO
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+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
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+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
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+ register "gen3_dec" = "0x000c03e1" # UART3/4
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+ register "gen3_dec" = "0x000c03e1" # UART3
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+ register "gen4_dec" = "0x000c02e1" # UART4
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+
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+ # Enable "Intel Speed Shift Technology"
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+ register "speed_shift_enable" = "1"
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@ -874,7 +876,7 @@ index 0000000..dbb589f
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+ register "ScsSdCardEnabled" = "0"
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+ register "SkipExtGfxScan" = "1"
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+ register "Device4Enable" = "1"
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+ register "SaGv" = "SaGv_Enabled"
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+ register "SaGv" = "SaGv_Disabled"
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+
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+ # Disable SGX
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+ register "sgx_enable" = "0" # SGX is broken in coreboot
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@ -889,7 +891,8 @@ index 0000000..dbb589f
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+ register "pirqg_routing" = "PCH_IRQ11"
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+ register "pirqh_routing" = "PCH_IRQ11"
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+
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+ register "SataMode" = "0"
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+ # SATA configuration
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+ register "SataMode" = "0" # AHCI
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+ register "EnableSata" = "1"
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+ register "SataSalpSupport" = "1"
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+ register "SataPortsEnable" = "{ \
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@ -914,52 +917,56 @@ index 0000000..dbb589f
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+ [7] = 0, \
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+ }"
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+
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+ # USB related
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+ register "SsicPortEnable" = "1"
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+ # superspeed_inter-chip_supplement (SSIC) disabled
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+ register "SsicPortEnable" = "0"
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+
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+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # OTG
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+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Touch Pad
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+ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # OTG
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+ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # Touch Pad
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+ # USB configuration
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+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3
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+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3
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+ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ?
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+ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ?
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+
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+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # OTG
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+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Touch Pad
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+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5
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+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5
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+
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+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # OTG
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+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Touch Pad
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+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1
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+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1
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+
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+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # OTG
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+ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # Touch Pad
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+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
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+ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
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+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
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+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
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+
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+ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # OTG
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+ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # Touch Pad
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+ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
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+ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
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+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
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+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
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+
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+ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # Touch Pad
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+ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0)
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+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
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+
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+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB
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+
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+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # OTG
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+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # M.2 WWAN
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+
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+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" # OTG
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+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # M.2 WWAN
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+
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+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" # M.2 WWAN
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+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB
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+
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+ # LPC
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+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
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+
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+ # Enable PCIE slot
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+ # PCIe configuration
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+ # Enable JPCIE1
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+ register "PcieRpEnable[0]" = "1"
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+ register "PcieRpClkReqSupport[0]" = "0"
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+
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+ # Enable PCIE slot
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+ # Enable ASpeed PCI bridge
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+ register "PcieRpEnable[2]" = "1"
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+ register "PcieRpClkReqSupport[2]" = "0"
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+
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+ # Enable PCIE slot
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+ # Enable X550T
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+ register "PcieRpEnable[4]" = "1"
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+ register "PcieRpClkReqSupport[4]" = "0"
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+
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+ # Enable M.2
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+ register "PcieRpEnable[8]" = "1"
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+ register "PcieRpClkReqSupport[8]" = "0"
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+
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+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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+ register "PmConfigSlpS3MinAssert" = "0x02"
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@ -973,75 +980,65 @@ index 0000000..dbb589f
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+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
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+ register "PmConfigSlpAMinAssert" = "0x03"
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+
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+
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+ # VR Settings Configuration for 4 Domains
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+ #+----------------+-------+-------+-------+-------+
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+ #| Domain/Setting | SA | IA | GTUS | GTS |
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+ #+----------------+-------+-------+-------+-------+
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+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
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+ #| Psi2Threshold | 5A | 5A | 5A | 5A |
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+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
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+ #| Psi3Enable | 1 | 1 | 1 | 1 |
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+ #| Psi4Enable | 1 | 1 | 1 | 1 |
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+ #| ImonSlope | 0 | 0 | 0 | 0 |
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+ #| ImonOffset | 0 | 0 | 0 | 0 |
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+ #| IccMax | 7A | 34A | 35A | 35A |
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+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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+ #+----------------+-------+-------+-------+-------+
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+ # ICC_MAX = 0 (Auto)
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+ # Voltage limit 1.52V (not used on KBL-S and KBL-DT)
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+ # Disable PS4 powerstate in S0ix, thus no package C10 support
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+ # psi threshold is using FSP default values
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+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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+ .vr_config_enable = 1, \
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+ .psi1threshold = 0x50, \
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+ .psi2threshold = 0x10, \
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+ .psi3threshold = 0x4, \
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+ .psi1threshold = VR_CFG_AMP(20),
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+ .psi2threshold = VR_CFG_AMP(5),
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+ .psi3threshold = VR_CFG_AMP(1),
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+ .psi3enable = 1, \
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+ .psi4enable = 1, \
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+ .psi4enable = 0, \
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+ .imon_slope = 0x0, \
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+ .imon_offset = 0x0, \
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+ .icc_max = 0x1C, \
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+ .voltage_limit = 0x5F0 \
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+ .icc_max = 0, \
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+ .voltage_limit = 1520 \
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+ }"
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+
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+ register "domain_vr_config[VR_IA_CORE]" = "{
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+ .vr_config_enable = 1, \
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+ .psi1threshold = 0x50, \
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+ .psi2threshold = 0x14, \
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+ .psi3threshold = 0x4, \
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+ .psi1threshold = VR_CFG_AMP(20),
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+ .psi2threshold = VR_CFG_AMP(5),
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+ .psi3threshold = VR_CFG_AMP(1),
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+ .psi3enable = 1, \
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+ .psi4enable = 1, \
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+ .psi4enable = 0, \
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+ .imon_slope = 0x0, \
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+ .imon_offset = 0x0, \
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+ .icc_max = 0x88, \
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+ .voltage_limit = 0x5F0 \
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+ .icc_max = 0, \
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+ .voltage_limit = 1520 \
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+ }"
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+
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+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
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+ .vr_config_enable = 1, \
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+ .psi1threshold = 0x50, \
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+ .psi2threshold = 0x14, \
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+ .psi3threshold = 0x4, \
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+ .psi1threshold = VR_CFG_AMP(20),
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+ .psi2threshold = VR_CFG_AMP(5),
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+ .psi3threshold = VR_CFG_AMP(1),
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+ .psi3enable = 1, \
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+ .psi4enable = 1, \
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+ .psi4enable = 0, \
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+ .imon_slope = 0x0, \
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+ .imon_offset = 0x0, \
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+ .icc_max = 0x8C ,\
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+ .voltage_limit = 0x5F0 \
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+ .icc_max = 0 ,\
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+ .voltage_limit = 1520 \
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+ }"
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+
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+ register "domain_vr_config[VR_GT_SLICED]" = "{
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+ .vr_config_enable = 1, \
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+ .psi1threshold = 0x50, \
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+ .psi2threshold = 0x14, \
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+ .psi3threshold = 0x4, \
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+ .psi1threshold = VR_CFG_AMP(20),
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+ .psi2threshold = VR_CFG_AMP(5),
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+ .psi3threshold = VR_CFG_AMP(1),
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+ .psi3enable = 1, \
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+ .psi4enable = 1, \
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+ .psi4enable = 0, \
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+ .imon_slope = 0x0, \
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+ .imon_offset = 0x0, \
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+ .icc_max = 0x8C, \
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+ .voltage_limit = 0x5F0 \
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+ .icc_max = 0, \
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+ .voltage_limit = 1520 \
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+ }"
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+
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+ # Send an extra VR mailbox command for the PS4 exit issue
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+ register "SendVrMbxCmd" = "2"
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+ # No extra VR mailbox command
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+ register "SendVrMbxCmd" = "0"
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+
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+ # Lock Down
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+ register "common_soc_config" = "{
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@ -1052,14 +1049,14 @@ index 0000000..dbb589f
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+ device lapic 0 on end
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+ end
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+ device domain 0 on
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+ device pci 00.0 on end # Host Bridge
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+ device pci 01.0 on end # PCI Slot
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+ device pci 00.0 on end # Host Bridge
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+ device pci 01.0 on end # unused
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+ device pci 01.1 on
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+ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
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+ end # PCIE Slot (JPCIE1)
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+ device pci 14.0 on end # USB xHCI
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+ device pci 14.2 on end # Thermal Subsystem
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+ device pci 16.0 on end # Management Engine Interface 1
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+ device pci 14.0 on end # USB xHCI
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+ device pci 14.2 on end # Thermal Subsystem
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+ device pci 16.0 on end # Management Engine Interface 1
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+ device pci 16.1 on end # Management Engine Interface 2
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+ device pci 17.0 on end # SATA
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+ device pci 1c.0 on
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@ -1067,17 +1064,22 @@ index 0000000..dbb589f
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+ end # PCI Express Port 1 (Slot JPCIE1)
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+ device pci 1c.2 on
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+ device pci 00.0 on
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+ device pci 00.0 on end #Aspeed 2400 VGA
|
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+ device pci 00.0 on end # Aspeed 2400 VGA
|
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+ end
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+ end # PCI Express Port 3
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+ device pci 1c.4 on
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+ device pci 00.0 on end # 10GBE
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+ device pci 00.1 on end # 10GBE
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+ device pci 00.0 on end # 10GBE
|
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+ device pci 00.1 on end # 10GBE
|
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+ end # PCI Express Port 5
|
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+ device pci 1d.0 on
|
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+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
|
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+ end # PCI Express Port 9
|
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+ device pci 1f.0 on
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+ chip drivers/ipmi
|
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+ device pnp ca2.0 on
|
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+ end # IPMI KCS
|
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+ # On cold boot it takes a while for the BMC to start the IPMI service
|
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+ register "wait_for_bmc" = "1"
|
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+ register "bmc_boot_timeout" = "60"
|
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+ device pnp ca2.0 on end # IPMI KCS
|
||||
+ end
|
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+ chip superio/common
|
||||
+ device pnp 2e.0 on
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||||
@ -1096,7 +1098,7 @@ index 0000000..dbb589f
|
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+ io 0x62 = 0xa10
|
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+ io 0x64 = 0xa20
|
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+ io 0x66 = 0xa30
|
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+ irq 0x70 = 0
|
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+ irq 0x70 = 0xb
|
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+ end
|
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+ device pnp 2e.5 on # Keyboard
|
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+ io 0x60 = 0x60
|
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@ -1105,18 +1107,16 @@ index 0000000..dbb589f
|
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+ irq 0x72 = 0xc
|
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+ end
|
||||
+ device pnp 2e.7 on # GPIO
|
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+ irq 0x70 = 0
|
||||
+ end
|
||||
+ device pnp 2e.b on # SUART3
|
||||
+ io 0x60 = 0x3e8
|
||||
+ irq 0x70 = 6
|
||||
+ irq 0x70 = 4
|
||||
+ end
|
||||
+ device pnp 2e.c on # SUART4
|
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+ io 0x60 = 0x2e8
|
||||
+ irq 0x70 = 5
|
||||
+ irq 0x70 = 3
|
||||
+ end
|
||||
+ device pnp 2e.d on # iLPC2AHB
|
||||
+ irq 0x70 = 0
|
||||
+ end
|
||||
+ device pnp 2e.e on # Mailbox
|
||||
+ io 0x60 = 0xa40
|
||||
@ -1129,10 +1129,10 @@ index 0000000..dbb589f
|
||||
+ device pnp 0c31.0 on end
|
||||
+ end
|
||||
+ end # LPC Interface
|
||||
+ device pci 1f.1 off end # P2SB
|
||||
+ device pci 1f.2 on end # Power Management Controller
|
||||
+ device pci 1f.4 on end # SMBus
|
||||
+ device pci 1f.5 on end # SPI Controller
|
||||
+ device pci 1f.1 on end # P2SB
|
||||
+ device pci 1f.2 on end # Power Management Controller
|
||||
+ device pci 1f.4 on end # SMBus
|
||||
+ device pci 1f.5 on end # SPI Controller
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd
|
||||
|
||||
Loading…
Reference in New Issue
Block a user