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modules/coreboot: bump 4.12 build option to 4.13

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- update module hash and blobs hash
- drop patches no longer needed; migrate those that remain
- adjust Librem Mini/Mini v2 board configs

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
This commit is contained in:
Matt DeVillier 2020-12-03 19:15:15 -06:00
parent a81ae6ed5b
commit 883ac669a8
No known key found for this signature in database
GPG Key ID: 2BBB776A35B978FD
10 changed files with 9 additions and 2548 deletions
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2
boards/librem_mini/librem_mini.config
View File

@ -3,7 +3,7 @@ CONFIG_LINUX_CONFIG=config/linux-librem_common.config
CONFIG_COREBOOT_CONFIG=config/coreboot-librem_mini.config
export CONFIG_COREBOOT=y
export CONFIG_COREBOOT_VERSION=4.12
export CONFIG_COREBOOT_VERSION=4.13
export CONFIG_LINUX_VERSION=5.4.69
export CONFIG_PURISM_BLOBS=y

2
boards/librem_mini_v2/librem_mini_v2.config
View File

@ -3,7 +3,7 @@ CONFIG_LINUX_CONFIG=config/linux-librem_common.config
CONFIG_COREBOOT_CONFIG=config/coreboot-librem_mini_v2.config
export CONFIG_COREBOOT=y
export CONFIG_COREBOOT_VERSION=4.12
export CONFIG_COREBOOT_VERSION=4.13
export CONFIG_LINUX_VERSION=5.4.69
export CONFIG_PURISM_BLOBS=y

8
modules/coreboot
View File

@ -11,10 +11,10 @@ else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.11"
coreboot_hash := 97fd859b4c39a25534fe33c30eb86e54a233952e08a024c55858d11598a8ad87
coreboot-blobs_hash := aa7855c5bd385b3360dadc043ea6bc93f564e6e4840d9b3ee5b9e696bbd055db
coreboot_depends := $(if $(CONFIG_PURISM_BLOBS), purism-blobs)
else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.12"
coreboot_version := 4.12
coreboot_hash := edcad000ee9b73183c396ea76155629b3d27c693e0f1ae83e3424c4d936e2be2
coreboot-blobs_hash := 4735ee6850d55d1e65dee8b08cc9b28b8af00b42acf31365f5d9545406579104
else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.13"
coreboot_version := 4.13
coreboot_hash := 4779da645a25ddebc78f1bd2bd0b740fb1e6479572648d4650042a2b9502856a
coreboot-blobs_hash := 060656b46a7859d038ddeec3f7e086e85f146a50b280c4babec23c1188264dc8
coreboot_depends := $(if $(CONFIG_PURISM_BLOBS), purism-blobs)
else
$(error "$(BOARD): does not specify coreboot version under CONFIG_COREBOOT_VERSION")

799
patches/coreboot-4.12/0002-mb-purism-librem_whl-Add-new-board-Librem-Mini-WHL-U.patch
View File

@ -1,799 +0,0 @@
From fcb25d39b270cdd21da3748e2d8f578b405f9a82 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@puri.sm>
Date: Fri, 26 Jun 2020 00:21:39 -0500
Subject: [PATCH] mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
Add new librem_whl baseboard and Librem Mini variant
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
---
src/mainboard/purism/librem_whl/Kconfig | 61 +++++
src/mainboard/purism/librem_whl/Kconfig.name | 3 +
src/mainboard/purism/librem_whl/Makefile.inc | 10 +
.../purism/librem_whl/acpi/mainboard.asl | 16 ++
.../purism/librem_whl/board_info.txt | 8 +
src/mainboard/purism/librem_whl/devicetree.cb | 223 +++++++++++++++++
src/mainboard/purism/librem_whl/dsdt.asl | 26 ++
src/mainboard/purism/librem_whl/ramstage.c | 16 ++
src/mainboard/purism/librem_whl/romstage.c | 52 ++++
.../librem_whl/variants/librem_mini/gpio.c | 229 ++++++++++++++++++
.../variants/librem_mini/hda_verb.c | 33 +++
.../librem_mini/include/variant/gpio.h | 11 +
13 files changed, 688 insertions(+)
create mode 100644 src/mainboard/purism/librem_whl/Kconfig
create mode 100644 src/mainboard/purism/librem_whl/Kconfig.name
create mode 100644 src/mainboard/purism/librem_whl/Makefile.inc
create mode 100644 src/mainboard/purism/librem_whl/acpi/mainboard.asl
create mode 100644 src/mainboard/purism/librem_whl/board_info.txt
create mode 100644 src/mainboard/purism/librem_whl/devicetree.cb
create mode 100644 src/mainboard/purism/librem_whl/dsdt.asl
create mode 100644 src/mainboard/purism/librem_whl/ramstage.c
create mode 100644 src/mainboard/purism/librem_whl/romstage.c
create mode 100644 src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
create mode 100644 src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c
create mode 100644 src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h
diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_whl/Kconfig
new file mode 100644
index 0000000000..f7662a0e72
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/Kconfig
@@ -0,0 +1,61 @@
+config BOARD_PURISM_BASEBOARD_LIBREM_WHL
+ def_bool n
+ select BOARD_ROMSIZE_KB_16384
+ select DRIVERS_GENERIC_CBFS_SERIAL
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select NO_UART_ON_SUPERIO
+ select SOC_INTEL_COMMON_BLOCK_HDA
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_WHISKEYLAKE
+ select SPD_READ_BY_WORD
+ select USE_LEGACY_8254_TIMER
+
+if BOARD_PURISM_BASEBOARD_LIBREM_WHL
+
+config MAINBOARD_DIR
+ string
+ default "purism/librem_whl"
+
+config MAINBOARD_FAMILY
+ string
+ default "Librem Mini" if BOARD_PURISM_LIBREM_MINI
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Librem Mini" if BOARD_PURISM_LIBREM_MINI
+
+config VARIANT_DIR
+ string
+ default "librem_mini" if BOARD_PURISM_LIBREM_MINI
+
+config CBFS_SIZE
+ hex
+ default 0x800000
+
+config MAX_CPUS
+ int
+ default 8
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config VGA_BIOS_ID
+ string
+ default "8086,3ea0"
+
+config PXE_ROM_ID
+ string
+ default "10ec,8168"
+
+# This platform has limited means to display POST codes
+config NO_POST
+ default y
+
+endif
diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_whl/Kconfig.name
new file mode 100644
index 0000000000..41a4003102
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_PURISM_LIBREM_MINI
+ bool "Librem Mini"
+ select BOARD_PURISM_BASEBOARD_LIBREM_WHL
diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_whl/Makefile.inc
new file mode 100644
index 0000000000..c03db05423
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/Makefile.inc
@@ -0,0 +1,10 @@
+##
+##
+##
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += ramstage.c
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_whl/acpi/mainboard.asl
new file mode 100644
index 0000000000..999030d2e5
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.LPCB) {
+
+ Device (AC)
+ {
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { LPCB })
+ Name (ACFG, One)
+
+ Method (_PSR, 0, NotSerialized)
+ {
+ Return (ACFG)
+ }
+ }
+}
diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_whl/board_info.txt
new file mode 100644
index 0000000000..e72dcdf2b7
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Purism
+Board name: librem_whl
+Category: desktop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb
new file mode 100644
index 0000000000..e67d910322
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/devicetree.cb
@@ -0,0 +1,223 @@
+chip soc/intel/cannonlake
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+ # Disable s0ix
+ register "s0ix_enable" = "0"
+
+ # PM Timer Enabled
+ register "PmTimerDisabled" = "0"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+ # Power limit
+ register "tdp_pl1_override" = "15"
+ register "tdp_pl2_override" = "25"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable Enhanced Intel SpeedStep
+ register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+ register "SaGv" = "SaGv_Enabled"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+ # Serial I/O
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # SATA
+ register "SataMode" = "Sata_AHCI"
+ register "SataSalpSupport" = "0"
+ register "SataPortsEnable[0]" = "1" # 2.5"
+ register "SataPortsEnable[2]" = "1" # m.2
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+
+ # Audio
+ register "PchHdaDspEnable" = "0"
+ register "PchHdaAudioLinkHda" = "1"
+ register "PchHdaAudioLinkDmic0" = "0"
+ register "PchHdaAudioLinkDmic1" = "0"
+ register "PchHdaAudioLinkSsp0" = "0"
+ register "PchHdaAudioLinkSsp1" = "0"
+ register "PchHdaAudioLinkSsp2" = "0"
+ register "PchHdaAudioLinkSndw1" = "0"
+ register "PchHdaAudioLinkSndw2" = "0"
+ register "PchHdaAudioLinkSndw3" = "0"
+ register "PchHdaAudioLinkSndw4" = "0"
+
+ # USB
+ register "SsicPortEnable" = "0"
+
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper
+ register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
+ register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
+ register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
+
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
+ register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
+ register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
+
+ # All SRCCLKREQ pins mapped directly
+ register "PcieClkSrcClkReq[0]" = "0"
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieClkSrcClkReq[5]" = "5"
+
+ # Set all SRCCLKREQ pins as free-use
+ register "PcieClkSrcUsage[0]" = "0x80"
+ register "PcieClkSrcUsage[1]" = "0x80"
+ register "PcieClkSrcUsage[2]" = "0x80"
+ register "PcieClkSrcUsage[3]" = "0x80"
+ register "PcieClkSrcUsage[4]" = "0x80"
+ register "PcieClkSrcUsage[5]" = "0x80"
+
+ # PCI Express Root Port #8 x1, Clock 2 (WLAN)
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+
+ # PCI Express Root Port #10 x1, Clock 3 (LAN)
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpLtrEnable[9]" = "0"
+
+ # PCI Express Root port #13 x4, Clock 1 (NVMe)
+ register "PcieRpEnable[12]" = "1"
+ register "PcieRpLtrEnable[12]" = "1"
+
+ # Misc
+ register "Device4Enable" = "1"
+ # HECI must be enabled w/HAP disable else S3 issues
+ register "HeciEnabled" = "1"
+ register "Heci3Enabled" = "0"
+ register "AcousticNoiseMitigation" = "1"
+ register "satapwroptimize" = "1"
+
+ # Power
+ register "PchPmSlpS3MinAssert" = "3" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "2" # 500ms
+ register "PchPmSlpAMinAssert" = "4" # 2s
+
+ # Thermal
+ register "tcc_offset" = "12"
+
+ # Serial IRQ Mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+ # Disable deep Sx states
+ register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+ register "gpe0_dw0" = "PMC_GPP_C"
+ register "gpe0_dw1" = "PMC_GPP_D"
+ register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # SA Thermal device
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 on end # PCI Express Port 8 (WLAN)
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 on end # PCI Express Port 10 (LAN)
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 on end # PCI Express Port 13 (NVMe)
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on end # LPC Bridge
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 off end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl
new file mode 100644
index 0000000000..296be17b35
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ #include <soc/intel/cannonlake/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c
new file mode 100644
index 0000000000..3479c0d3ed
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/ramstage.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ size_t num_gpios;
+ const struct pad_config *gpio_table = variant_gpio_table(&num_gpios);
+ cnl_configure_pads(gpio_table, num_gpios);
+
+ /* Limit SATA speed to 3Gbps */
+ params->SataSpeedLimit = 2;
+}
diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c
new file mode 100644
index 0000000000..9f8d600950
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/romstage.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+
+ /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+ .spd[0] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa0},
+ },
+ .spd[1] = {.read_type = NOT_EXISTING},
+ .spd[2] = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {.spd_smbus_address = 0xa4},
+ },
+ .spd[3] = {.read_type = NOT_EXISTING},
+
+ /*
+ * Rcomp resistor values. These values represent the resistance in
+ * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+ * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ */
+ .rcomp_resistor = { 121, 81, 100 },
+
+ /* Rcomp target values */
+ .rcomp_targets = { 100, 40, 20, 20, 26 },
+
+ /*
+ * Indicates whether memory is interleaved.
+ * Set to 1 for an interleaved design,
+ * set to 0 for non-interleaved design.
+ */
+ .dq_pins_interleaved = 1,
+
+ /*
+ * VREF_CA configuration.
+ * Set to 0 VREF_CA goes to both CH_A and CH_B,
+ * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+ * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+ */
+ .vref_ca_config = 2,
+
+ /* Early Command Training */
+ .ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}
diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
new file mode 100644
index 0000000000..a5b2dcafa3
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variant/gpio.h>
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+
+/* ------- GPIO Group GPP_A ------- */
+
+_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0000), /* RCIN# */
+_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */
+_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */
+_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */
+_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */
+_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0000), /* LFRAME# */
+_PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0000), /* SERIRQ */
+_PAD_CFG_STRUCT(GPP_A7, 0x84000200, 0x0000), /* PIRQA# */
+_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0000), /* CLKRUN# */
+_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */
+_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */
+_PAD_CFG_STRUCT(GPP_A11, 0x40880201, 0x0000), /* PME# */
+_PAD_CFG_STRUCT(GPP_A12, 0x84000201, 0x0000), /* BM_BUSY# */
+_PAD_CFG_STRUCT(GPP_A13, 0x84000201, 0x0000), /* SUSWARN#/SUSPWRDNACK*/
+_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0000), /* SUS_STAT# */
+_PAD_CFG_STRUCT(GPP_A15, 0x84000201, 0x0000), /* SUSACK# */
+_PAD_CFG_STRUCT(GPP_A16, 0x84000200, 0x3000), /* SD_1P8_SEL */
+_PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0000), /* SD_VDD1_PWR_EN# */
+_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x3000), /* ISH_GP0 */
+_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x3000), /* ISH_GP1 */
+_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x3000), /* ISH_GP2 */
+_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x3000), /* ISH_GP3 */
+_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x3000), /* ISH_GP4 */
+_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x3000), /* ISH_GP5 */
+
+/* ------- GPIO Group GPP_B ------- */
+
+_PAD_CFG_STRUCT(GPP_B0, 0x84000700, 0x0000), /* Reserved */
+_PAD_CFG_STRUCT(GPP_B1, 0x84000700, 0x0000), /* Reserved */
+_PAD_CFG_STRUCT(GPP_B2, 0x84000201, 0x0000), /* VRALERT# */
+_PAD_CFG_STRUCT(GPP_B3, 0x84000201, 0x0000), /* CPU_GP2 */
+_PAD_CFG_STRUCT(GPP_B4, 0x84000201, 0x0000), /* CPU_GP3 */
+_PAD_CFG_STRUCT(GPP_B5, 0x44000300, 0x0000), /* SRCCLKREQ0# */
+_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x0000), /* SRCCLKREQ1# */
+_PAD_CFG_STRUCT(GPP_B7, 0x44000300, 0x0000), /* SRCCLKREQ2# */
+_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0000), /* SRCCLKREQ3# */
+_PAD_CFG_STRUCT(GPP_B9, 0x44000300, 0x0000), /* SRCCLKREQ4# */
+_PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0000), /* SRCCLKREQ5# */
+_PAD_CFG_STRUCT(GPP_B11, 0x84000201, 0x0000), /* EXT_PWR_GATE# */
+_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0000), /* SLP_S0# */
+_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0000), /* PLTRST# */
+_PAD_CFG_STRUCT(GPP_B14, 0x84000201, 0x0000), /* SPKR */
+_PAD_CFG_STRUCT(GPP_B15, 0x80000701, 0x0000), /* GSPI0_CS0# */
+_PAD_CFG_STRUCT(GPP_B16, 0x84000601, 0x0000), /* GSPI0_CLK */
+_PAD_CFG_STRUCT(GPP_B17, 0x44000502, 0x0000), /* GSPI0_MISO */
+_PAD_CFG_STRUCT(GPP_B18, 0x84000601, 0x0000), /* GSPI0_MOSI */
+_PAD_CFG_STRUCT(GPP_B19, 0x84000400, 0x0000), /* GSPI1_CS0# */
+_PAD_CFG_STRUCT(GPP_B20, 0x84000400, 0x0000), /* GSPI1_CLK */
+_PAD_CFG_STRUCT(GPP_B21, 0x84000402, 0x0000), /* GSPI1_MISO */
+_PAD_CFG_STRUCT(GPP_B22, 0x84000400, 0x0000), /* GSPI1_MOSI */
+_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x0000), /* SML1ALERT# */
+
+/* ------- GPIO Group GPP_G ------- */
+
+_PAD_CFG_STRUCT(GPP_G0, 0x84000200, 0x0000), /* SD_CMD */
+_PAD_CFG_STRUCT(GPP_G1, 0x84000300, 0x0000), /* SD_DATA0 */
+_PAD_CFG_STRUCT(GPP_G2, 0x84000300, 0x0000), /* SD_DATA1 */
+_PAD_CFG_STRUCT(GPP_G3, 0x84000300, 0x0000), /* SD_DATA2 */
+_PAD_CFG_STRUCT(GPP_G4, 0x84000300, 0x0000), /* SD_DATA3 */
+_PAD_CFG_STRUCT(GPP_G5, 0x84000300, 0x3000), /* SD3_CD# */
+_PAD_CFG_STRUCT(GPP_G6, 0x84000300, 0x0000), /* SD3_CLK */
+_PAD_CFG_STRUCT(GPP_G7, 0x84000300, 0x1000), /* SD3_WP */
+
+/* ------- GPIO Group GPP_D ------- */
+
+_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x0000), /* SPI1_CS# */
+_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x0000), /* SPI1_CLK */
+_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x0000), /* SPI1_MISO */
+_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x0000), /* SPI1_MOSI */
+_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x0000), /* IMGCLKOUT0 */
+_PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0000), /* ISH_I2C0_SDA */
+_PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0000), /* ISH_I2C0_SCL */
+_PAD_CFG_STRUCT(GPP_D7, 0x84000201, 0x0000), /* ISH_I2C1_SDA */
+_PAD_CFG_STRUCT(GPP_D8, 0x84000200, 0x0000), /* ISH_I2C1_SCL */
+_PAD_CFG_STRUCT(GPP_D9, 0x84000201, 0x0000), /* ISH_SPI_CS# */
+_PAD_CFG_STRUCT(GPP_D10, 0x84000201, 0x0000), /* ISH_SPI_CLK */
+_PAD_CFG_STRUCT(GPP_D11, 0x44000201, 0x3000), /* ISH_SPI_MISO */
+_PAD_CFG_STRUCT(GPP_D12, 0x42100102, 0x3000), /* ISH_SPI_MOSI */
+_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x0000), /* ISH_UART0_RXD */
+_PAD_CFG_STRUCT(GPP_D14, 0x84000201, 0x0000), /* ISH_UART0_TXD */
+_PAD_CFG_STRUCT(GPP_D15, 0x84000201, 0x0000), /* ISH_UART0_RTS# */
+_PAD_CFG_STRUCT(GPP_D16, 0x44000200, 0x0000), /* ISH_UART0_CTS# */
+_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0000), /* DMIC_CLK1 */
+_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0000), /* DMIC_DATA1 */
+_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0000), /* DMIC_CLK0 */
+_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0000), /* DMIC_DATA0 */
+_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0000), /* SPI1_IO2 */
+_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0000), /* SPI1_IO3 */
+_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0000), /* I2S_MCLK */
+
+/* ------- GPIO Group GPP_F ------- */
+
+_PAD_CFG_STRUCT(GPP_F0, 0x84000301, 0x0000), /* CNV_PA_BLANKING */
+_PAD_CFG_STRUCT(GPP_F1, 0x84000200, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F2, 0x84000201, 0x3000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F3, 0x84000200, 0x3000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x3000), /* CNV_BRI_DT */
+_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x3000), /* CNV_BRI_RSP */
+_PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x3000), /* CNV_RGI_DT */
+_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x3000), /* CNV_RGI_RSP */
+_PAD_CFG_STRUCT(GPP_F8, 0x44000300, 0x0000), /* CNV_MFUART2_RXD */
+_PAD_CFG_STRUCT(GPP_F9, 0x44000300, 0x0000), /* CNV_MFUART2_TXD */
+_PAD_CFG_STRUCT(GPP_F10, 0x84000201, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0000), /* EMMC_CMD */
+_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0000), /* EMMC_DATA0 */
+_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0000), /* EMMC_DATA1 */
+_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x0000), /* EMMC_DATA2 */
+_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x0000), /* EMMC_DATA3 */
+_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x0000), /* EMMC_DATA4 */
+_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x0000), /* EMMC_DATA5 */
+_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x0000), /* EMMC_DATA6 */
+_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x0000), /* EMMC_DATA7 */
+_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x0000), /* EMMC_RCLK */
+_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x0000), /* EMMC_CLK */
+_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0000), /* EMMC_RESET# */
+_PAD_CFG_STRUCT(GPP_F23, 0x44000700, 0x1000), /* A4WP_PRESENT */
+
+/* ------- GPIO Group GPP_H ------- */
+
+_PAD_CFG_STRUCT(GPP_H0, 0x44000300, 0x3000), /* I2S2_SCLK */
+_PAD_CFG_STRUCT(GPP_H1, 0x44000f00, 0x3000), /* CNV_RF_RESET# */
+_PAD_CFG_STRUCT(GPP_H2, 0x84000f00, 0x3000), /* MODEM_CLKREQ */
+_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x3000), /* I2S2_RXD */
+_PAD_CFG_STRUCT(GPP_H4, 0x84000300, 0x0000), /* I2C2_SDA */
+_PAD_CFG_STRUCT(GPP_H5, 0x84000300, 0x0000), /* I2C2_SCL */
+_PAD_CFG_STRUCT(GPP_H6, 0x84000702, 0x0000), /* I2C3_SDA */
+_PAD_CFG_STRUCT(GPP_H7, 0x84000702, 0x0000), /* I2C3_SCL */
+_PAD_CFG_STRUCT(GPP_H8, 0x84000702, 0x0000), /* I2C4_SDA */
+_PAD_CFG_STRUCT(GPP_H9, 0x84000702, 0x0000), /* I2C4_SCL */
+_PAD_CFG_STRUCT(GPP_H10, 0x84000603, 0x0000), /* I2C5_SDA */
+_PAD_CFG_STRUCT(GPP_H11, 0x84000603, 0x0000), /* I2C5_SCL */
+_PAD_CFG_STRUCT(GPP_H12, 0x84000201, 0x0000), /* M2_SKT2_CFG0 */
+_PAD_CFG_STRUCT(GPP_H13, 0x84000201, 0x0000), /* M2_SKT2_CFG1 */
+_PAD_CFG_STRUCT(GPP_H14, 0x84000200, 0x0000), /* M2_SKT2_CFG2 */
+_PAD_CFG_STRUCT(GPP_H15, 0x84000201, 0x0000), /* M2_SKT2_CFG3 */
+_PAD_CFG_STRUCT(GPP_H16, 0x84000201, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_H17, 0x84000201, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_H18, 0x84000700, 0x0000), /* CPU_C10_GATE# */
+_PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x0000), /* TIME_SYNC0 */
+_PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000), /* IMGCLKOUT1 */
+_PAD_CFG_STRUCT(GPP_H21, 0x84000200, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_H23, 0x84000200, 0x0000), /* GPIO */
+
+/* ------- GPIO Group GPD ------- */
+
+_PAD_CFG_STRUCT(GPD0, 0x44000702, 0x0000), /* BATLOW# */
+_PAD_CFG_STRUCT(GPD1, 0x44000702, 0x3c00), /* ACPRESENT */
+_PAD_CFG_STRUCT(GPD2, 0x44000702, 0x3c00), /* LAN_WAKE# */
+_PAD_CFG_STRUCT(GPD3, 0x44000702, 0x3000), /* PRWBTN# */
+_PAD_CFG_STRUCT(GPD4, 0x44000600, 0x0000), /* SLP_S3# */
+_PAD_CFG_STRUCT(GPD5, 0x44000600, 0x0000), /* SLP_S4# */
+_PAD_CFG_STRUCT(GPD6, 0x44000600, 0x0000), /* SLP_A# */
+_PAD_CFG_STRUCT(GPD7, 0x44000200, 0x0000), /* GPIO */
+_PAD_CFG_STRUCT(GPD8, 0x44000700, 0x0000), /* SUSCLK */
+_PAD_CFG_STRUCT(GPD9, 0x44000700, 0x0000), /* SLP_WLAN# */
+_PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0000), /* SLP_S5# */
+_PAD_CFG_STRUCT(GPD11, 0x44000600, 0x0000), /* LANPHYPC */
+
+/* ------- GPIO Group GPP_C ------- */
+
+_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0000), /* SMBCLK */
+_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x0000), /* SMBDATA */
+_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x0000), /* SMBALERT# */
+_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0000), /* SML0CLK */
+_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0000), /* SML0DATA */
+_PAD_CFG_STRUCT(GPP_C5, 0x84000201, 0x0000), /* SML0ALERT# */
+_PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x0000), /* SML1CLK */
+_PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x0000), /* SML1DATA */
+_PAD_CFG_STRUCT(GPP_C8, 0x84000201, 0x0000), /* UART0_RXD */
+_PAD_CFG_STRUCT(GPP_C9, 0x84000201, 0x0000), /* UART0_TXD */
+_PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0000), /* UART0_RTS# */
+_PAD_CFG_STRUCT(GPP_C11, 0x84000201, 0x0000), /* UART0_CTS# */
+_PAD_CFG_STRUCT(GPP_C12, 0x84000603, 0x0000), /* UART1_RXD */
+_PAD_CFG_STRUCT(GPP_C13, 0x84000700, 0x0000), /* UART1_TXD */
+_PAD_CFG_STRUCT(GPP_C14, 0x84000700, 0x0000), /* UART1_RTS# */
+_PAD_CFG_STRUCT(GPP_C15, 0x84000702, 0x0000), /* UART1_CTS# */
+_PAD_CFG_STRUCT(GPP_C16, 0x84000402, 0x0000), /* I2C0_SDA */
+_PAD_CFG_STRUCT(GPP_C17, 0x84000402, 0x0000), /* I2C0_SCL */
+_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0000), /* I2C1_SDA */
+_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0000), /* I2C1_SCL */
+_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0000), /* UART2_RXD */
+_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0000), /* UART2_TXD */
+_PAD_CFG_STRUCT(GPP_C22, 0x84000201, 0x0000), /* UART2_RTS# */
+_PAD_CFG_STRUCT(GPP_C23, 0x40100102, 0x1000), /* UART2_CTS# */
+
+/* ------- GPIO Group GPP_E ------- */
+
+_PAD_CFG_STRUCT(GPP_E0, 0x84000300, 0x0000), /* SATAXPCIE0 */
+_PAD_CFG_STRUCT(GPP_E1, 0x84000300, 0x0000), /* SATAXPCIE1 */
+_PAD_CFG_STRUCT(GPP_E2, 0x84000502, 0x3000), /* SATAXPCIE2 */
+_PAD_CFG_STRUCT(GPP_E3, 0x82040102, 0x0000), /* CPU_GP0 */
+_PAD_CFG_STRUCT(GPP_E4, 0x84000201, 0x0000), /* SATA_DEVSLP0 */
+_PAD_CFG_STRUCT(GPP_E5, 0x84000300, 0x0000), /* SATA_DEVSLP1 */
+_PAD_CFG_STRUCT(GPP_E6, 0x84000300, 0x0000), /* SATA_DEVSLP2 */
+_PAD_CFG_STRUCT(GPP_E7, 0x82000102, 0x0000), /* CPU_GP1 */
+_PAD_CFG_STRUCT(GPP_E8, 0x84000700, 0x0000), /* SATALED# */
+_PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000), /* USB2_OC0# */
+_PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000), /* USB2_OC1# */
+_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0000), /* USB2_OC2# */
+_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0000), /* USB2_OC3# */
+_PAD_CFG_STRUCT(GPP_E13, 0x84000700, 0x0000), /* DDPB_HPD0 */
+_PAD_CFG_STRUCT(GPP_E14, 0x84000702, 0x0000), /* DDPC_HPD1 */
+_PAD_CFG_STRUCT(GPP_E15, 0x84000201, 0x0000), /* DDPD_HPD2 */
+_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E17, 0x84000700, 0x0000), /* EDP_HPD */
+_PAD_CFG_STRUCT(GPP_E18, 0x84000702, 0x0000), /* DPPB_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E19, 0x84000602, 0x0000), /* DPPB_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E20, 0x84000700, 0x0000), /* DPPC_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E21, 0x84000602, 0x0000), /* DPPC_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E22, 0x84000702, 0x0000), /* DPPD_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E23, 0x84000602, 0x0000), /* DPPD_CTRLDATA */
+
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c
new file mode 100644
index 0000000000..c3daf3c5ed
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */
+ 0x10ec0000, /* Subsystem ID */
+ 11, /* Number of entries */
+
+ AZALIA_SUBVENDOR(0, 0x10ec0000),
+ AZALIA_PIN_CFG(0, 0x12, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x15, 0x01214010),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19130),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40422201),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of entries */
+
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(2, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h
new file mode 100644
index 0000000000..9094b0419d
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+const struct pad_config *variant_gpio_table(size_t *num);
+
+#endif
--
2.20.1

67
patches/coreboot-4.12/0003-soc-intel-common-block-systemagent-memmap.c-Align-ca.patch
View File

@ -1,67 +0,0 @@
From c46fd7eb28c6513613f672c78f8786e28ee5235d Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 1 Oct 2020 22:50:12 +0200
Subject: [PATCH] soc/intel/common/block/systemagent/memmap.c: Align cached region
When asked to place cbmem_top(), FSP does not seem to care about
alignment. It can return an address that is MTRR poison, which will
exhaust all variable MTRRs when trying to set up caching for CBMEM.
This will make memory-mapped flash and TSEG caching fail as well.
Safeguard against this by aligning the region to cache to half of its
size, and move it upwards to compensate. It is assumed that caching
memory above the provided bootloader TOLUM address is inconsequential.
TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error
messages in console. The boot process also feels more fluid.
Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
src/soc/intel/common/block/systemagent/memmap.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index 985f2c4814..27870b0cf7 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -6,6 +6,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <intelblocks/systemagent.h>
+#include <types.h>
/*
* Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs):
@@ -55,18 +56,18 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- uintptr_t top_of_ram;
+ /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */
+ uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB);
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
- * Instruct postcar to cache 16 megs under cbmem top which is
+ * Instruct postcar to cache 16 megs below cbmem top which is
* a safe bet to cover ramstage.
*/
- top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+ postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
--
2.20.1

141
patches/coreboot-4.12/0004-mb-purism-librem_whl-rename-to-librem_cnl.patch
View File

@ -1,141 +0,0 @@
From f18a3aa83e12050c1cf18e79371e48c24962fe65 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@puri.sm>
Date: Thu, 29 Oct 2020 20:30:08 -0500
Subject: [PATCH] mb/purism/librem_whl: rename to librem_cnl
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake,
rename the baseboard so that boards using other 'cannonlake family' SoCs
(e.g., Cometlake) can be added with minimal confusion.
Rename the mainboard dir and baseboard name, and adjust any references
to them.
Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
.../purism/{librem_whl => librem_cnl}/Kconfig | 6 +++---
.../purism/{librem_whl => librem_cnl}/Kconfig.name | 2 +-
.../purism/{librem_whl => librem_cnl}/Makefile.inc | 0
.../{librem_whl => librem_cnl}/acpi/mainboard.asl | 0
.../{librem_whl => librem_cnl}/board_info.txt | 2 +-
.../purism/{librem_whl => librem_cnl}/devicetree.cb | 0
.../purism/{librem_whl => librem_cnl}/dsdt.asl | 0
.../purism/{librem_whl => librem_cnl}/ramstage.c | 0
.../purism/{librem_whl => librem_cnl}/romstage.c | 0
.../variants/librem_mini/gpio.c | 0
.../variants/librem_mini/hda_verb.c | 0
.../variants/librem_mini/include/variant/gpio.h | 0
13 files changed, 5 insertions(+), 5 deletions(-)
rename src/mainboard/purism/{librem_whl => librem_cnl}/Kconfig (89%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/Kconfig.name (55%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/Makefile.inc (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/acpi/mainboard.asl (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/board_info.txt (85%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/devicetree.cb (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/dsdt.asl (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/ramstage.c (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/romstage.c (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/gpio.c (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/hda_verb.c (100%)
rename src/mainboard/purism/{librem_whl => librem_cnl}/variants/librem_mini/include/variant/gpio.h (100%)
diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
similarity index 89%
rename from src/mainboard/purism/librem_whl/Kconfig
rename to src/mainboard/purism/librem_cnl/Kconfig
index f7662a0e72..453490b7d2 100644
--- a/src/mainboard/purism/librem_whl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -1,4 +1,4 @@
-config BOARD_PURISM_BASEBOARD_LIBREM_WHL
+config BOARD_PURISM_BASEBOARD_LIBREM_CNL
def_bool n
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_CBFS_SERIAL
@@ -12,11 +12,11 @@ config BOARD_PURISM_BASEBOARD_LIBREM_WHL
select SPD_READ_BY_WORD
select USE_LEGACY_8254_TIMER
-if BOARD_PURISM_BASEBOARD_LIBREM_WHL
+if BOARD_PURISM_BASEBOARD_LIBREM_CNL
config MAINBOARD_DIR
string
- default "purism/librem_whl"
+ default "purism/librem_cnl"
config MAINBOARD_FAMILY
string
diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name
similarity index 55%
rename from src/mainboard/purism/librem_whl/Kconfig.name
rename to src/mainboard/purism/librem_cnl/Kconfig.name
index 41a4003102..326165ba07 100644
--- a/src/mainboard/purism/librem_whl/Kconfig.name
+++ b/src/mainboard/purism/librem_cnl/Kconfig.name
@@ -1,3 +1,3 @@
config BOARD_PURISM_LIBREM_MINI
bool "Librem Mini"
- select BOARD_PURISM_BASEBOARD_LIBREM_WHL
+ select BOARD_PURISM_BASEBOARD_LIBREM_CNL
diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc
similarity index 100%
rename from src/mainboard/purism/librem_whl/Makefile.inc
rename to src/mainboard/purism/librem_cnl/Makefile.inc
diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_cnl/acpi/mainboard.asl
similarity index 100%
rename from src/mainboard/purism/librem_whl/acpi/mainboard.asl
rename to src/mainboard/purism/librem_cnl/acpi/mainboard.asl
diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_cnl/board_info.txt
similarity index 85%
rename from src/mainboard/purism/librem_whl/board_info.txt
rename to src/mainboard/purism/librem_cnl/board_info.txt
index e72dcdf2b7..ca61edd88d 100644
--- a/src/mainboard/purism/librem_whl/board_info.txt
+++ b/src/mainboard/purism/librem_cnl/board_info.txt
@@ -1,5 +1,5 @@
Vendor name: Purism
-Board name: librem_whl
+Board name: librem_cnl
Category: desktop
Release year: 2020
ROM package: SOIC-8
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb
similarity index 100%
rename from src/mainboard/purism/librem_whl/devicetree.cb
rename to src/mainboard/purism/librem_cnl/devicetree.cb
diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_cnl/dsdt.asl
similarity index 100%
rename from src/mainboard/purism/librem_whl/dsdt.asl
rename to src/mainboard/purism/librem_cnl/dsdt.asl
diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_cnl/ramstage.c
similarity index 100%
rename from src/mainboard/purism/librem_whl/ramstage.c
rename to src/mainboard/purism/librem_cnl/ramstage.c
diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c
similarity index 100%
rename from src/mainboard/purism/librem_whl/romstage.c
rename to src/mainboard/purism/librem_cnl/romstage.c
diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
similarity index 100%
rename from src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
rename to src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
similarity index 100%
rename from src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c
rename to src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c
diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h
similarity index 100%
rename from src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h
rename to src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h
--
2.20.1

1462
patches/coreboot-4.12/0005-mb-purism-librem_cnl-Adjust-in-preparation-for-new-v.patch
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File diff suppressed because it is too large Load Diff

70
patches/coreboot-4.12/0006-mb-purism-librem_cnl-Add-new-variant-Librem-Mini-v2.patch
View File

@ -1,70 +0,0 @@
From df8425fbe588efdec7f4ebe8831a12c27b8bbbb8 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@puri.sm>
Date: Mon, 2 Nov 2020 17:19:53 -0600
Subject: [PATCH] mb/purism/librem_cnl: Add new variant 'Librem Mini v2'
Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.
Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
---
src/mainboard/purism/librem_cnl/Kconfig | 7 +++++--
src/mainboard/purism/librem_cnl/Kconfig.name | 5 +++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index 464350ce8c..39d57e6da4 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -20,15 +20,16 @@ config MAINBOARD_DIR
config MAINBOARD_FAMILY
string
- default "Librem Mini" if BOARD_PURISM_LIBREM_MINI
+ default "Librem Mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2
config MAINBOARD_PART_NUMBER
string
default "Librem Mini" if BOARD_PURISM_LIBREM_MINI
+ default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2
config VARIANT_DIR
string
- default "librem_mini" if BOARD_PURISM_LIBREM_MINI
+ default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2
config DEVICETREE
string
@@ -37,6 +38,7 @@ config DEVICETREE
config CBFS_SIZE
hex
default 0x800000 if BOARD_PURISM_LIBREM_MINI
+ default 0xA00000 if BOARD_PURISM_LIBREM_MINI_V2
config MAX_CPUS
int
@@ -53,6 +55,7 @@ config DIMM_SPD_SIZE
config VGA_BIOS_ID
string
default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI
+ default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2
config PXE_ROM_ID
string
diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name
index 83f1495ab1..455e79ffe0 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig.name
+++ b/src/mainboard/purism/librem_cnl/Kconfig.name
@@ -2,3 +2,8 @@ config BOARD_PURISM_LIBREM_MINI
bool "Librem Mini"
select BOARD_PURISM_BASEBOARD_LIBREM_CNL
select SOC_INTEL_WHISKEYLAKE
+
+config BOARD_PURISM_LIBREM_MINI_V2
+ bool "Librem Mini v2"
+ select BOARD_PURISM_BASEBOARD_LIBREM_CNL
+ select SOC_INTEL_COMETLAKE
--
2.20.1

6
patches/coreboot-4.12/0001-soc-cannonlake-me.c-Always-print-ME-status.patch → patches/coreboot-4.13/0001-soc-cannonlake-me.c-Always-print-ME-status.patch
View File

@ -1,4 +1,4 @@
From 32e60b698d33eec419bf0e4865ece7b86ea1355a Mon Sep 17 00:00:00 2001
From ce401513ac08b0c5b121e0f9c4bb38ee6e99a47d Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@puri.sm>
Date: Fri, 19 Jun 2020 17:02:22 -0500
Subject: [PATCH] soc/cannonlake/me.c: Always print ME status
@ -13,7 +13,7 @@ Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
1 file changed, 3 deletions(-)
diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c
index a51b702e6a..3fae0bf534 100644
index 7bbe1ae730..4fe5a96ade 100644
--- a/src/soc/intel/cannonlake/me.c
+++ b/src/soc/intel/cannonlake/me.c
@@ -103,9 +103,6 @@ void dump_me_status(void *unused)
@ -24,7 +24,7 @@ index a51b702e6a..3fae0bf534 100644
- return;
-
hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
hfsts2.raw = me_read_config32(PCI_ME_HFSTS2);
hfsts2.data = me_read_config32(PCI_ME_HFSTS2);
hfsts3.data = me_read_config32(PCI_ME_HFSTS3);
--
2.20.1

0
patches/coreboot-4.12/0010-cross-compiler-support.patch → patches/coreboot-4.13/0010-cross-compiler-support.patch
View File