mirror of
https://github.com/linuxboot/heads.git
synced 2025-02-20 09:16:21 +00:00
modules/coreboot: remove support for coreboot 4.15
patches/coreboot-4.15: remove patches for coreboot 4.15 No boards depend on it and is affected by CVE-2022-29264 Signed-off-by: Daniel Pineda <daniel.pineda@puri.sm>
This commit is contained in:
Daniel Pineda
parent
1cab17ae30
commit
8150e300ee
@ -29,12 +29,6 @@ else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.13"
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coreboot_hash := 4779da645a25ddebc78f1bd2bd0b740fb1e6479572648d4650042a2b9502856a
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coreboot-blobs_hash := 060656b46a7859d038ddeec3f7e086e85f146a50b280c4babec23c1188264dc8
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coreboot_depends := $(if $(CONFIG_PURISM_BLOBS), purism-blobs)
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else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.15"
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coreboot_version := 4.15
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coreboot_hash := 20e6aaa6dd0eaec7753441c799711d1b4630e3ca709536386f2242ac2c8a1ec5
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coreboot-blobs_hash := c0e2d8006da226208ba274a44895d102cb2879cf139cc67bba5f62e67b871f6d
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coreboot_depends := $(if $(CONFIG_PURISM_BLOBS), purism-blobs)
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EXTRA_FLAGS := -fdebug-prefix-map=$(pwd)=heads -gno-record-gcc-switches -Wno-error=packed-not-aligned -Wno-error=address-of-packed-member
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else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.17"
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coreboot_version := 4.17
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coreboot_hash := 95da11d1c6a450385101a68799258a398ce965f4e46cce6fe8d5ebd74e50c125
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@ -1,36 +0,0 @@
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From cf41f0aa19329802676feed24df1ba9697d065a1 Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Mon, 18 May 2020 14:02:27 -0500
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Subject: [PATCH 1/9] soc/skylake/me.c: Print status regardless of device
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enable state
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Checking the CSE device status before printing means it will skip
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printing for devices with the ME disabled, leaving the user no easy
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way to verify the ME is properly disabled. Remove the check.
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Test: build/boot Librem 13v4, verify ME status printed as expected
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on device with disabled/neutered ME.
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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Change-Id: Iaa4f4a369d878a52136c3479027443ea4e731a36
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---
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src/soc/intel/skylake/me.c | 3 ---
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1 file changed, 3 deletions(-)
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diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
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index 89491f89c3..08aceb3f83 100644
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--- a/src/soc/intel/skylake/me.c
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+++ b/src/soc/intel/skylake/me.c
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@@ -188,9 +188,6 @@ void intel_me_status(void)
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union me_hfsts3 hfs3;
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union me_hfsts6 hfs6;
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- if (!is_cse_enabled())
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- return;
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-
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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hfs2.data = me_read_config32(PCI_ME_HFSTS2);
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hfs3.data = me_read_config32(PCI_ME_HFSTS3);
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--
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2.30.2
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@ -1,36 +0,0 @@
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From d7775b8a5a018930eece1ce9e50cb00863845d2e Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Fri, 19 Jun 2020 17:02:22 -0500
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Subject: [PATCH 2/9] soc/cannonlake/me.c: Print status regardless of device
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enable state
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Checking the CSE device status before printing means it will skip
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printing for devices with the ME disabled, leaving the user no easy
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way to verify the ME is properly disabled. Remove the check.
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Test: build/boot Librem Mini, verify ME status printed as expected
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on device with disabled/neutered ME.
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Change-Id: I939333199aa699039fec727beb094e4eb2ad7149
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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---
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src/soc/intel/cannonlake/me.c | 3 ---
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1 file changed, 3 deletions(-)
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diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c
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index 7bbe1ae730..4fe5a96ade 100644
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--- a/src/soc/intel/cannonlake/me.c
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+++ b/src/soc/intel/cannonlake/me.c
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@@ -103,9 +103,6 @@ void dump_me_status(void *unused)
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union me_hfsts5 hfsts5;
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union me_hfsts6 hfsts6;
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- if (!is_cse_enabled())
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- return;
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-
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hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
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hfsts2.data = me_read_config32(PCI_ME_HFSTS2);
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hfsts3.data = me_read_config32(PCI_ME_HFSTS3);
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--
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2.30.2
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@ -1,47 +0,0 @@
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From cda3f1eb067e07e4a7110ef482912273d690be9e Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Tue, 25 Jan 2022 12:16:44 -0600
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Subject: [PATCH 5/9] soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master]
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updated the FSP binaries/headers for Comet Lake, which included a change
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moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing
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UDP in FSP-S was left in and deprecated, which allowed the change to go
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unnoticed until it was discovered that hotplug wasn't working.
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Since other related platforms (WHL, CFL) share the SoC code but use
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different FSP packages, add the setting of the PcieRpHotPlug UPD to
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romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'.
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Test: build/boot Purism Librem 14, verify WiFi killswitch operates
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as expected / WiFi is re-enabled when turning switch to on position.
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Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Reviewed-by: Nico Huber <nico.h@gmx.de>
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---
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src/soc/intel/cannonlake/romstage/fsp_params.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
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index 8cb6c92a65..0b63bd52f9 100644
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--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
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+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
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@@ -59,6 +59,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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m_cfg->EnableC6Dram = config->enable_c6dram;
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#if CONFIG(SOC_INTEL_COMETLAKE)
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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+ memcpy(tconfig->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(tconfig->PcieRpHotPlug));
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#else
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m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
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#endif
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--
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2.30.2
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@ -1,66 +0,0 @@
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From 6d4b0be203b99e66043991796e1fdbbba26ba3ce Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Tue, 25 Jan 2022 12:41:49 -0600
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Subject: [PATCH 6/9] soc/intel/skylake: move heci_init() from bootblock to
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romstage
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Aligns with all other soc/intel/common platforms calling heci_init().
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Test: build/boot Purism Librem 13v2
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Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378
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Reviewed-by: Subrata Banik <subratabanik@google.com>
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Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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---
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src/soc/intel/skylake/bootblock/pch.c | 4 ----
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src/soc/intel/skylake/romstage/romstage.c | 3 +++
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2 files changed, 3 insertions(+), 4 deletions(-)
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diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
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index 1685e43e0e..ec60cabbea 100644
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--- a/src/soc/intel/skylake/bootblock/pch.c
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+++ b/src/soc/intel/skylake/bootblock/pch.c
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@@ -2,7 +2,6 @@
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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-#include <intelblocks/cse.h>
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#include <intelblocks/dmi.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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@@ -141,8 +140,5 @@ void bootblock_pch_init(void)
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enable_rtc_upper_bank();
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- /* initialize Heci interface */
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- heci_init(HECI1_BASE_ADDRESS);
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-
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gspi_early_bar_init();
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}
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diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
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index 30f65eae01..7e891b19f8 100644
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--- a/src/soc/intel/skylake/romstage/romstage.c
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+++ b/src/soc/intel/skylake/romstage/romstage.c
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@@ -4,6 +4,7 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <fsp/util.h>
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+#include <intelblocks/cse.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/smbus.h>
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#include <memory_info.h>
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@@ -127,6 +128,8 @@ void mainboard_romstage_entry(void)
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systemagent_early_init();
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/* Program SMBus base address and enable it */
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smbus_common_init();
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+ /* initialize Heci interface */
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+ heci_init(HECI1_BASE_ADDRESS);
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ps = pmc_get_power_state();
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s3wake = pmc_fill_power_state(ps) == ACPI_S3;
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fsp_memory_init(s3wake);
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--
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2.30.2
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@ -1,36 +0,0 @@
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From 237477540b03e3066ce0ffe51310a06f91e89252 Mon Sep 17 00:00:00 2001
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From: Subrata Banik <subratabanik@google.com>
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Date: Wed, 26 Jan 2022 01:42:18 +0530
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Subject: [PATCH 7/9] soc/intel/common/cse: Drop CSE library usage in bootblock
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This patch drops the CSE common code block from getting compiled
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in bootblock without any SoC code using heci communication so
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early in the boot flow.
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BUG=none
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TEST=Able to build brya, purism/librem_skl without any compilation issue.
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Signed-off-by: Subrata Banik <subratabanik@google.com>
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Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7
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Reviewed-on: https://review.coreboot.org/c/coreboot/+/61382
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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---
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src/soc/intel/common/block/cse/Makefile.inc | 1 -
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1 file changed, 1 deletion(-)
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diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
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index eac7d90424..339ede11b8 100644
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--- a/src/soc/intel/common/block/cse/Makefile.inc
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+++ b/src/soc/intel/common/block/cse/Makefile.inc
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@@ -1,4 +1,3 @@
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-bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
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--
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2.30.2
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@ -1,38 +0,0 @@
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From 8d416eec8ba1d929b7afd4718161ae0c1c4e24e3 Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Tue, 25 Jan 2022 19:48:38 -0600
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Subject: [PATCH 8/9] soc/intel/common/cse: skip heci_init() if HECI1 is
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disabled
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If the HECI1 PCI device is disabled, either via devicetree or other
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method (HAP, me_cleaner), then we don't want/need to program a BAR,
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set the PCI config, or call heci_reset(), as the latter will result
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in a 15s timeout delay when booting.
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Test: build/boot Purism Librem 13v2, verify heci_reset()
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timeout delay is no longer present.
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Change-Id: I0babe417173d10e37327538dc9e7aae980225367
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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---
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src/soc/intel/common/block/cse/cse.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
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index f37ff9589e..eb4597b82d 100644
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--- a/src/soc/intel/common/block/cse/cse.c
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+++ b/src/soc/intel/common/block/cse/cse.c
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@@ -91,6 +91,10 @@ void heci_init(uintptr_t tempbar)
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u16 pcireg;
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+ /* Check if device enabled */
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+ if (!is_cse_enabled())
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+ return;
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+
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/* Assume it is already initialized, nothing else to do */
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if (get_cse_bar(dev))
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return;
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--
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2.30.2
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@ -1,34 +0,0 @@
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From 7e8b5f1b32f2d7b12ed3df191d3f4b1f1254489c Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Tue, 25 Jan 2022 19:52:44 -0600
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Subject: [PATCH 9/9] mb/purism/librem_skl: disable HECI PCI device
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As all librem_skl devices ship with the ME disabled via HAP bit and ME
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firmware "neutralized" via me_cleaner, the HECI1 PCI device should be
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marked off/disabled to ensure that heci_reset() is not called at the end
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of heci_init(), as this causes a 15s timeout delay when booting
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(introduced in commit cb2fd20 [soc/intel/common: Add HECI Reset flow in
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the CSE driver]).
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Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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---
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src/mainboard/purism/librem_skl/devicetree.cb | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
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index 5efb1e2aed..68fa343b3c 100644
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--- a/src/mainboard/purism/librem_skl/devicetree.cb
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+++ b/src/mainboard/purism/librem_skl/devicetree.cb
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@@ -162,7 +162,7 @@ chip soc/intel/skylake
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device pci 14.1 on end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 14.3 off end # Camera
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- device pci 16.0 on end # Management Engine Interface 1
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+ device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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--
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2.30.2
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|
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Block a user