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On KGPE-D16 boards, ensure linux-kgpe-d16*.config are up-to-date by:
cp config/linux.. ./build/linux*/.config cd build/linux* make savedefconfig cp defconfig ../../config/linux.. Resulting in only linux-kgpe-d16_workstation.config being updated. For KGPE-D16 workstation boards: Remove `console=tty0` from `CONFIG_BOOT_KERNEL_ADD` as was blocking Qubes graphical installer (CLI installer was launched). Comment out `export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"` to provide a more desktop like experience. Removed 0001-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch as already exists as 0000-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch Added 0020-kgpe-d16_measured-boot-support.patch for coreboot 4.11 Fix TPM errors when microcode is measured by initialising TPM earlier and loading the microcode later. Thanks to Michał Żygowski <miczyg1> for condition suggestion: `if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM) && boot_cpu())` Locate bootblock location and size with CBFS API. Credit to: Michał Żygowski <miczyg1>
This commit is contained in:
parent
9f751f11fe
commit
572f5b3414
@ -57,13 +57,13 @@ export CONFIG_ERROR_BG_COLOR="--background-gradient 0 0 0 150 0 0"
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#Dual output to local console (tty0) and OpenBmc (ttyS1)
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#Dual output to local console (tty0) and OpenBmc (ttyS1)
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#export CONFIG_BOOT_KERNEL_ADD="nohz=on console=ttyS1,115200n8 console=tty0"
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#export CONFIG_BOOT_KERNEL_ADD="nohz=on console=ttyS1,115200n8 console=tty0"
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#Single output to tty0
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#Single output to tty0
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export CONFIG_BOOT_KERNEL_ADD="nohz=on console=tty0 nouveau.config=NvForcePost=1"
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export CONFIG_BOOT_KERNEL_ADD="nohz=on nouveau.config=NvForcePost=1"
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#export CONFIG_BOOT_RECOVERY_SERIAL="/dev/ttyS0"
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#export CONFIG_BOOT_RECOVERY_SERIAL="/dev/ttyS0"
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#export CONFIG_BOOT_STATIC_IP=192.168.2.3
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#export CONFIG_BOOT_STATIC_IP=192.168.2.3
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export CONFIG_BOOT_REQ_HASH=n
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export CONFIG_BOOT_REQ_HASH=n
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export CONFIG_BOOT_REQ_ROLLBACK=n
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export CONFIG_BOOT_REQ_ROLLBACK=n
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export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"
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#export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"
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export CONFIG_BOOT_DEV="/dev/sda1"
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export CONFIG_BOOT_DEV="/dev/sda1"
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export CONFIG_USB_BOOT_DEV="/dev/sdb1"
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export CONFIG_USB_BOOT_DEV="/dev/sdb1"
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export CONFIG_FLASHROM_OPTIONS="--force --noverify -p internal"
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export CONFIG_FLASHROM_OPTIONS="--force --noverify -p internal"
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@ -58,13 +58,13 @@ export CONFIG_ERROR_BG_COLOR="--background-gradient 0 0 0 150 0 0"
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#Dual output to local console (tty0) and OpenBmc (ttyS1)
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#Dual output to local console (tty0) and OpenBmc (ttyS1)
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#export CONFIG_BOOT_KERNEL_ADD="nohz=on console=ttyS1,115200n8 console=tty0"
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#export CONFIG_BOOT_KERNEL_ADD="nohz=on console=ttyS1,115200n8 console=tty0"
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#Single output to tty0
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#Single output to tty0
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export CONFIG_BOOT_KERNEL_ADD="nohz=on console=tty0 nouveau.config=NvForcePost=1"
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export CONFIG_BOOT_KERNEL_ADD="nohz=on nouveau.config=NvForcePost=1"
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#export CONFIG_BOOT_RECOVERY_SERIAL="/dev/ttyS0"
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#export CONFIG_BOOT_RECOVERY_SERIAL="/dev/ttyS0"
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#export CONFIG_BOOT_STATIC_IP=192.168.2.3
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#export CONFIG_BOOT_STATIC_IP=192.168.2.3
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export CONFIG_BOOT_REQ_HASH=n
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export CONFIG_BOOT_REQ_HASH=n
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export CONFIG_BOOT_REQ_ROLLBACK=n
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export CONFIG_BOOT_REQ_ROLLBACK=n
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export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"
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#export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"
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export CONFIG_BOOT_DEV="/dev/sda1"
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export CONFIG_BOOT_DEV="/dev/sda1"
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export CONFIG_USB_BOOT_DEV="/dev/sdb1"
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export CONFIG_USB_BOOT_DEV="/dev/sdb1"
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export CONFIG_FLASHROM_OPTIONS="--force --noverify -p internal"
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export CONFIG_FLASHROM_OPTIONS="--force --noverify -p internal"
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@ -56,7 +56,6 @@ CONFIG_KEXEC_FILE=y
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CONFIG_PHYSICAL_ALIGN=0x1000000
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CONFIG_PHYSICAL_ALIGN=0x1000000
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# CONFIG_MODIFY_LDT_SYSCALL is not set
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# CONFIG_MODIFY_LDT_SYSCALL is not set
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# CONFIG_SUSPEND is not set
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# CONFIG_SUSPEND is not set
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CONFIG_ACPI_VIDEO=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_MSI=y
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# CONFIG_HT_IRQ is not set
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# CONFIG_HT_IRQ is not set
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CONFIG_PCI_IOV=y
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CONFIG_PCI_IOV=y
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@ -179,15 +178,15 @@ CONFIG_I2C_MUX_REG=m
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# CONFIG_I2C_HELPER_AUTO is not set
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# CONFIG_I2C_HELPER_AUTO is not set
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CONFIG_I2C_SLAVE=y
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CONFIG_I2C_SLAVE=y
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CONFIG_PTP_1588_CLOCK=y
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CONFIG_PTP_1588_CLOCK=y
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# CONFIG_HWMON is not set
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# CONFIG_X86_PKG_TEMP_THERMAL is not set
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# CONFIG_X86_PKG_TEMP_THERMAL is not set
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CONFIG_MFD_SYSCON=y
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CONFIG_MFD_SYSCON=y
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CONFIG_DRM=y
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CONFIG_DRM=y
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CONFIG_DRM_RADEON=y
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CONFIG_DRM_AMDGPU=y
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CONFIG_DRM_NOUVEAU=y
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CONFIG_DRM_AST=y
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CONFIG_DRM_AST=y
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CONFIG_FB_VESA=y
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CONFIG_FB_VESA=y
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CONFIG_BACKLIGHT_LCD_SUPPORT=y
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# CONFIG_LCD_CLASS_DEVICE is not set
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# CONFIG_LCD_CLASS_DEVICE is not set
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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# CONFIG_BACKLIGHT_GENERIC is not set
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# CONFIG_BACKLIGHT_GENERIC is not set
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CONFIG_FRAMEBUFFER_CONSOLE=y
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CONFIG_FRAMEBUFFER_CONSOLE=y
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CONFIG_USB=y
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CONFIG_USB=y
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@ -200,7 +199,6 @@ CONFIG_USB_OHCI_HCD_PLATFORM=m
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CONFIG_USB_UHCI_HCD=m
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CONFIG_USB_UHCI_HCD=m
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CONFIG_USB_STORAGE=m
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CONFIG_USB_STORAGE=m
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_CLASS=y
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# CONFIG_X86_PLATFORM_DEVICES is not set
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CONFIG_INTEL_IOMMU=y
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CONFIG_INTEL_IOMMU=y
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CONFIG_INTEL_IOMMU_SVM=y
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CONFIG_INTEL_IOMMU_SVM=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PHY=y
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@ -324,6 +322,3 @@ CONFIG_CRC8=m
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CONFIG_XZ_DEC_TEST=m
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CONFIG_XZ_DEC_TEST=m
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CONFIG_CORDIC=m
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CONFIG_CORDIC=m
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CONFIG_IRQ_POLL=y
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CONFIG_IRQ_POLL=y
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CONFIG_DRM_NOUVEAU=y
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CONFIG_DRM_RADEON=y
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CONFIG_DRM_AMDGPU=y
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@ -1,47 +0,0 @@
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From 06f2fcc0ffc1a903f304d8a3382f3a57163989a1 Mon Sep 17 00:00:00 2001
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From: Jacob Garber <jgarber1@ualberta.ca>
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Date: Mon, 4 Nov 2019 09:35:15 -0700
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Subject: [PATCH] cpu/x86/smm: Use PRIxPTR to print uintptr_t
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Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This
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fixes a compilation error when targeting x86_64 or using Clang 9.0.0.
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Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f
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Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
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Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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---
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src/cpu/x86/smm/tseg_region.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
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index a8b8bb7b9a..5b5c5729d5 100644
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--- a/src/cpu/x86/smm/tseg_region.c
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+++ b/src/cpu/x86/smm/tseg_region.c
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@@ -17,6 +17,7 @@
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#include <cpu/x86/smm.h>
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#include <stage_cache.h>
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#include <types.h>
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+#include <inttypes.h>
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/*
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* Subregions within SMM
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@@ -88,11 +89,11 @@ void smm_list_regions(void)
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return;
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printk(BIOS_DEBUG, "SMM Memory Map\n");
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- printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size);
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+ printk(BIOS_DEBUG, "SMRAM : 0x%" PRIxPTR " 0x%zx\n", base, size);
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for (i = 0; i < SMM_SUBREGION_NUM; i++) {
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if (smm_subregion(i, &base, &size))
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continue;
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- printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
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+ printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size);
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}
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}
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--
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2.21.1
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@ -0,0 +1,67 @@
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diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
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index 637ec42109..8a92f88375 100644
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--- a/src/mainboard/asus/kgpe-d16/romstage.c
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+++ b/src/mainboard/asus/kgpe-d16/romstage.c
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@@ -46,6 +46,12 @@
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#include <cbmem.h>
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#include <types.h>
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+#include <security/tpm/tss.h>
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+#include <security/tpm/tspi.h>
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+#include <program_loading.h>
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+#include <smp/node.h>
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+#include <cbfs.h>
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+
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#include "cpu/amd/quadcore/quadcore.c"
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#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
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@@ -547,7 +553,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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power_on_reset = 1;
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initialize_mca(1, power_on_reset);
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- update_microcode(val);
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post_code(0x33);
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@@ -573,6 +578,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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sr5650_early_setup();
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sb7xx_51xx_early_setup();
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+ if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM) && boot_cpu()) {
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+ tpm_setup(0);
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+ tlcl_lib_init();
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+ }
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+
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+ update_microcode(val);
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+
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if (CONFIG(LOGICAL_CPUS)) {
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/* Core0 on each node is configured. Now setup any additional cores. */
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printk(BIOS_DEBUG, "start_other_cores()\n");
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@@ -687,6 +699,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707);
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pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
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pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
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+
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+ if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM)) {
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+ size_t bootblock_size = 0;
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+ const void *bootblock = cbfs_boot_map_with_leak("bootblock", 1, &bootblock_size);
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+ tlcl_measure(2, bootblock, bootblock_size);
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+
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+ extern char _romstage, _eromstage;
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+ tlcl_measure(2, &_romstage, &_eromstage - &_romstage);
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+ }
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+
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+
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}
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/**
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@@ -718,3 +741,9 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
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return 0;
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}
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+
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+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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+{
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+ if (CONFIG(MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
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+ tlcl_measure(2, (const void *) start, size);
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+}
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