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patches/coreboot-t480/85278-post-skylake-pr0.patch: remove xeon bits we are not interested into which are conflicting against coreboot upstream commit 2f1e4e5e8515dd350cc9d68b48d32a5b6b02ae6a
Signed-off-by: Thierry Laurion <insurgo@riseup.net>
This commit is contained in:
parent
7f673d4882
commit
32fc31bc6e
@ -424,54 +424,6 @@ index cd02745a9e..158b2fb691 100644
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tbt_finalize();
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if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
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heci1_disable();
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diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c
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index a7b3602744..f0cd8a1998 100644
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--- a/src/soc/intel/xeon_sp/finalize.c
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+++ b/src/soc/intel/xeon_sp/finalize.c
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@@ -59,7 +59,8 @@ static void soc_finalize(void *unused)
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if (!CONFIG(USE_PM_ACPI_TIMER))
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setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
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- apm_control(APM_CNT_FINALIZE);
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+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
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+ apm_control(APM_CNT_FINALIZE);
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if (CONFIG_MAX_SOCKET > 1) {
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/* This MSR is package scope but run for all cpus for code simplicity */
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diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c
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index a3d17b46c3..51a5cf5431 100644
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--- a/src/soc/intel/xeon_sp/lockdown.c
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+++ b/src/soc/intel/xeon_sp/lockdown.c
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@@ -6,25 +6,15 @@
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#include <soc/lockdown.h>
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#include <soc/pm.h>
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-static void lpc_lockdown_config(void)
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-{
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- /* Set BIOS Interface Lock, BIOS Lock */
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- lpc_set_bios_interface_lock_down();
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-
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- /* Only allow writes in SMM */
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- if (CONFIG(BOOTMEDIA_SMM_BWP)) {
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- lpc_set_eiss();
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- lpc_enable_wp();
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- }
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- lpc_set_lock_enable();
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-}
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-
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void soc_lockdown_config(int chipset_lockdown)
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{
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if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
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return;
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- lpc_lockdown_config();
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+ if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM))
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+ /* LPC/eSPI lock down configuration */
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+ lpc_lockdown_config(chipset_lockdown);
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+
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pmc_lockdown_config();
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sata_lockdown_config(chipset_lockdown);
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spi_lockdown_config(chipset_lockdown);
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--
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2.39.5
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