diff --git a/boards/kgpe-d16.config b/boards/kgpe-d16.config
new file mode 100644
index 00000000..af2e6f31
--- /dev/null
+++ b/boards/kgpe-d16.config
@@ -0,0 +1,32 @@
+# Configuration for a kgpe-d16 running non-Qubes
+CONFIG_COREBOOT=y
+CONFIG_COREBOOT_CONFIG=config/coreboot-kgpe-d16.config
+CONFIG_LINUX_CONFIG=config/linux-kgpe-d16.config
+
+CONFIG_CRYPTSETUP=y
+CONFIG_FLASHROM=y
+CONFIG_GPG=y
+CONFIG_KEXEC=y
+CONFIG_UTIL_LINUX=y
+CONFIG_LVM2=y
+CONFIG_MBEDTLS=y
+CONFIG_PCIUTILS=y
+CONFIG_POPT=y
+CONFIG_QRENCODE=y
+CONFIG_TPMTOTP=y
+CONFIG_DROPBEAR=y
+
+CONFIG_LINUX_USB=y
+CONFIG_LINUX_E1000E=y
+CONFIG_LINUX_PTY=y
+
+CONFIG_BOOTSCRIPT=/bin/generic-init
+
+CONFIG_BOOT_REQ_HASH=n
+CONFIG_BOOT_REQ_ROLLBACK=n
+CONFIG_BOOT_KERNEL_ADD="nohz=on console=ttyS1,115200n8 "
+CONFIG_BOOT_KERNEL_REMOVE=""
+CONFIG_BOOT_DEV="/dev/sda1"
+CONFIG_USB_BOOT_DEV="/dev/sdb1"
+CONFIG_BOOT_RECOVERY_SERIAL="/dev/ttyS0"
+CONFIG_BOOT_LOCAL=y
diff --git a/config/coreboot-kgpe-d16.config b/config/coreboot-kgpe-d16.config
new file mode 100644
index 00000000..e294e944
--- /dev/null
+++ b/config/coreboot-kgpe-d16.config
@@ -0,0 +1,714 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION="heads"
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+CONFIG_USE_OPTION_TABLE=y
+# CONFIG_STATIC_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+# CONFIG_COLLECT_TIMESTAMPS is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_RELOCATABLE_RAMSTAGE is not set
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_MEASURED_BOOT is not set
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADI is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASROCK is not set
+CONFIG_VENDOR_ASUS=y
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BACHMANN is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_DMP is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LINUTOP is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_LOWRISC is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WINNET is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="asus/kgpe-d16"
+CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16"
+CONFIG_IRQ_SLOT_COUNT=13
+CONFIG_MAINBOARD_VENDOR="ASUS"
+CONFIG_MAX_CPUS=32
+CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0
+CONFIG_CBFS_SIZE=0x1000000
+CONFIG_UART_FOR_CONSOLE=1
+CONFIG_APIC_ID_OFFSET=0x0
+CONFIG_HW_MEM_HOLE_SIZEK=0x100000
+CONFIG_MAX_PHYSICAL_CPUS=4
+# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set
+CONFIG_HT_CHAIN_END_UNITID_BASE=0x20
+CONFIG_HT_CHAIN_UNITID_BASE=0x0
+CONFIG_VGA_BIOS_ID="1a03,2000"
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_DIMM_SPD_SIZE=256
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_DCACHE_RAM_BASE=0xc2000
+CONFIG_DCACHE_RAM_SIZE=0x1e000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
+# CONFIG_BOARD_ASUS_A8N_E is not set
+# CONFIG_BOARD_ASUS_A8N_SLI is not set
+# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set
+# CONFIG_BOARD_ASUS_A8V_E_SE is not set
+# CONFIG_BOARD_ASUS_AM1I_A is not set
+# CONFIG_BOARD_ASUS_DSBF is not set
+# CONFIG_BOARD_ASUS_F2A85_M is not set
+# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
+# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
+# CONFIG_BOARD_ASUS_K8V_X is not set
+# CONFIG_BOARD_ASUS_KCMA_D8 is not set
+# CONFIG_BOARD_ASUS_KFSN4_DRE is not set
+# CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set
+CONFIG_BOARD_ASUS_KGPE_D16=y
+# CONFIG_BOARD_ASUS_M2N_E is not set
+# CONFIG_BOARD_ASUS_M2V_MX_SE is not set
+# CONFIG_BOARD_ASUS_M2V is not set
+# CONFIG_BOARD_ASUS_M4A78_EM is not set
+# CONFIG_BOARD_ASUS_M4A785M is not set
+# CONFIG_BOARD_ASUS_M4A785TM is not set
+# CONFIG_BOARD_ASUS_M5A88_V is not set
+# CONFIG_BOARD_ASUS_MEW_AM is not set
+# CONFIG_BOARD_ASUS_MEW_VM is not set
+# CONFIG_BOARD_ASUS_P2B_D is not set
+# CONFIG_BOARD_ASUS_P2B_DS is not set
+# CONFIG_BOARD_ASUS_P2B_F is not set
+# CONFIG_BOARD_ASUS_P2B_LS is not set
+# CONFIG_BOARD_ASUS_P2B is not set
+# CONFIG_BOARD_ASUS_P3B_F is not set
+# CONFIG_BOARD_ASUS_P5GC_MX is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xc0000000
+CONFIG_POST_IO=y
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_AGP_APERTURE_SIZE=0x4000000
+CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kgpe-d16/bootblock.c"
+CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f
+CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y
+CONFIG_MAX_REBOOT_CNT=10
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_POST_DEVICE=y
+# CONFIG_VBOOT is not set
+CONFIG_TPM_PIRQ=0x0
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_FMDFILE=""
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_TTYS0_LCS=3
+CONFIG_DRIVERS_UART_8250IO=y
+CONFIG_UDELAY_LAPIC_FIXED_FSB=200
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16"
+CONFIG_CPU_ADDR_BITS=48
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_PCIEXP_L1_SUB_STATE=y
+# CONFIG_NO_POST is not set
+CONFIG_BOARD_ROMSIZE_KB_2048=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_16384=y
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=16384
+CONFIG_ROM_SIZE=0x1000000
+# CONFIG_MAINBOARD_HAS_TPM2 is not set
+# CONFIG_SYSTEM_TYPE_LAPTOP is not set
+# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
+CONFIG_MMCONF_BUS_NUMBER=256
+CONFIG_RAMTOP=0x400000
+CONFIG_HEAP_SIZE=0xc0000
+CONFIG_RAMBASE=0x100000
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
+# CONFIG_SOC_BROADCOM_CYGNUS is not set
+# CONFIG_SOC_INTEL_GLK is not set
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c"
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c"
+CONFIG_TTYS0_BASE=0x2f8
+CONFIG_STACK_SIZE=0x1000
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_HPET_MIN_TICKS=0x14
+# CONFIG_SOC_INTEL_KABYLAKE is not set
+# CONFIG_SOC_LOWRISC_LOWRISC is not set
+# CONFIG_SOC_MARVELL_MVMAP2315 is not set
+CONFIG_TTYS0_BAUD=115200
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QC_IPQ40XX is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_SOC_ROCKCHIP_RK3399 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_DCACHE_BSP_STACK_SLUSH=0x4000
+CONFIG_DCACHE_AP_STACK_SIZE=0x500
+CONFIG_CPU_SOCKET_TYPE=0x15
+# CONFIG_EXT_RT_TBL_SUPPORT is not set
+CONFIG_CBB=0x0
+CONFIG_CDB=0x18
+CONFIG_XIP_ROM_SIZE=0x80000
+CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA=y
+CONFIG_DIMM_SUPPORT=0x0005
+CONFIG_LIFT_BSP_APIC_ID=y
+CONFIG_SET_FIDVID=y
+CONFIG_SET_FIDVID_DEBUG=y
+# CONFIG_SET_FIDVID_CORE0_ONLY is not set
+CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y
+CONFIG_CPU_AMD_MODEL_10XXX=y
+CONFIG_USE_LARGE_DCACHE=y
+CONFIG_NUM_IPI_STARTS=1
+CONFIG_SET_FIDVID_CORE_RANGE=0
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_S3_DATA_POS=0x0
+CONFIG_S3_DATA_SIZE=32768
+# CONFIG_CPU_AMD_PI is not set
+CONFIG_EXT_CONF_SUPPORT=y
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+CONFIG_SSE2=y
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+CONFIG_PARALLEL_CPU_INIT=y
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_LAPIC_MONOTONIC_TIMER is not set
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+CONFIG_TSC_SYNC_LFENCE=y
+# CONFIG_TSC_SYNC_MFENCE is not set
+# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
+CONFIG_LOGICAL_CPUS=y
+# CONFIG_SMM_TSEG is not set
+# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
+# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
+CONFIG_X86_AMD_FIXED_MTRRS=y
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+# CONFIG_SOC_SETS_MSRS is not set
+CONFIG_CACHE_AS_RAM=y
+# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set
+CONFIG_SMP=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_SSE=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+CONFIG_CPU_MICROCODE_MULTIPLE_FILES=y
+CONFIG_CPU_UCODE_BINARIES=""
+
+#
+# Northbridge
+#
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y
+# CONFIG_HT_CHAIN_DISTRIBUTE is not set
+# CONFIG_DIMM_FBDIMM is not set
+# CONFIG_DIMM_DDR2 is not set
+CONFIG_DIMM_DDR3=y
+CONFIG_DIMM_REGISTERED=y
+CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y
+# CONFIG_SVI_HIGH_FREQ is not set
+
+#
+# HyperTransport setup
+#
+# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set
+CONFIG_LIMIT_HT_DOWN_WIDTH_16=y
+# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set
+CONFIG_LIMIT_HT_UP_WIDTH_16=y
+# CONFIG_NO_MMCONF_SUPPORT is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_AMD_SB700=y
+CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
+# CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI is not set
+CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y
+# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set
+CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y
+CONFIG_SOUTHBRIDGE_AMD_SR5650=y
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
+# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
+
+#
+# Super I/O
+#
+# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set
+CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y
+CONFIG_SUPERIO_WINBOND_W83667HG_A=y
+
+#
+# Embedded Controllers
+#
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_UDK_2015_BINDING is not set
+# CONFIG_USE_SIEMENS_HWILIB is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_POWER8 is not set
+# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set
+# CONFIG_ARCH_VERSTAGE_POWER8 is not set
+# CONFIG_ARCH_ROMSTAGE_POWER8 is not set
+# CONFIG_ARCH_RAMSTAGE_POWER8 is not set
+# CONFIG_ARCH_RISCV is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_USE_MARCH_586 is not set
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+# CONFIG_ROMCC is not set
+# CONFIG_CBMEM_TOP_BACKUP is not set
+# CONFIG_LATE_CBMEM_INIT is not set
+# CONFIG_EARLY_EBDA_INIT is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
+# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_POSTCAR_STAGE is not set
+# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
+# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+
+#
+# Devices
+#
+CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
+CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
+# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
+CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+CONFIG_SMBUS_HAS_AUX_CHANNELS=y
+CONFIG_PCI=y
+CONFIG_MMCONF_SUPPORT=y
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+# CONFIG_GIC is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
+# CONFIG_RT8168_SET_LED_MODE is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
+# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+CONFIG_DRIVERS_UART=y
+# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set
+# CONFIG_NO_UART_ON_SUPERIO is not set
+# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
+# CONFIG_UART_OVERRIDE_REFCLK is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_DRIVERS_AMD_PI is not set
+CONFIG_DRIVERS_ASPEED_AST2050=y
+CONFIG_DRIVERS_ASPEED_AST_COMMON=y
+# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
+# CONFIG_DRIVERS_I2C_MAX98927 is not set
+# CONFIG_DRIVERS_I2C_PCF8523 is not set
+# CONFIG_DRIVERS_I2C_RT5663 is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_DRIVERS_I2C_RX6110SA is not set
+# CONFIG_I2C_TPM is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
+CONFIG_DRIVERS_I2C_W83795=y
+# CONFIG_INTEL_DDI is not set
+# CONFIG_INTEL_EDID is not set
+# CONFIG_INTEL_INT15 is not set
+# CONFIG_INTEL_GMA_ACPI is not set
+# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
+# CONFIG_DRIVER_INTEL_I210 is not set
+# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_USE_SAR is not set
+# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_DRIVER_PARADE_PS8640 is not set
+CONFIG_DRIVERS_MC146818=y
+CONFIG_MAINBOARD_HAS_LPC_TPM=y
+CONFIG_LPC_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
+# CONFIG_TPM_INIT_FAILURE_IS_FATAL is not set
+# CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT is not set
+# CONFIG_TPM_DEACTIVATE is not set
+CONFIG_VGA=y
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
+# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_SPI_TPM is not set
+# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+# CONFIG_COMMONLIB_STORAGE is not set
+
+#
+# Security
+#
+
+#
+# Verified Boot (vboot)
+#
+# CONFIG_ACPI_SATA_GENERATOR is not set
+# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
+# CONFIG_RTC is not set
+# CONFIG_TPM is not set
+CONFIG_TPM2=y
+# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set
+
+#
+# Console
+#
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_CONSOLE_SERIAL=y
+
+#
+# I/O mapped, 8250-compatible
+#
+
+#
+# Serial port base address = 0x2f8
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CMOS_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_ACPI_HUGE_LOWMEM_BACKUP=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y
+CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y
+CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+# CONFIG_HAVE_SMI_HANDLER is not set
+CONFIG_PCI_IO_CFG_EXT=y
+CONFIG_IOAPIC=y
+# CONFIG_USE_WATCHDOG_ON_BOOT is not set
+# CONFIG_GFXUMA is not set
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
+# CONFIG_COMMON_FADT is not set
+# CONFIG_ACPI_NHLT is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BAYOU is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_UBOOT is not set
+CONFIG_PAYLOAD_LINUX=y
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="../../build/kgpe-d16/bzImage"
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_LINUX_COMMAND_LINE="nohz=on console=ttyS1,115200n8 earlyprintk=ttyS1,115200"
+CONFIG_LINUX_INITRD="../../build/kgpe-d16/initrd.cpio.xz"
+# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
+
+#
+# Secondary Payloads
+#
+# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+# CONFIG_TINT_SECONDARY_PAYLOAD is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+CONFIG_HAVE_DEBUG_CAR=y
+# CONFIG_DEBUG_CAR is not set
+# CONFIG_DEBUG_PIRQ is not set
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_TRACE is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+CONFIG_ENABLE_APIC_EXT_ID=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
+# CONFIG_CREATE_BOARD_CHECKLIST is not set
+# CONFIG_MAKE_CHECKLIST_PUBLIC is not set
+# CONFIG_NO_XIP_EARLY_STAGES is not set
+CONFIG_EARLY_CBMEM_INIT=y
+# CONFIG_EARLY_CBMEM_LIST is not set
+CONFIG_BOOTBLOCK_CUSTOM=y
diff --git a/config/linux-kgpe-d16.config b/config/linux-kgpe-d16.config
new file mode 100644
index 00000000..46c643a8
--- /dev/null
+++ b/config/linux-kgpe-d16.config
@@ -0,0 +1,2670 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/x86 4.9.80 Kernel Configuration
+#
+CONFIG_64BIT=y
+CONFIG_X86_64=y
+CONFIG_X86=y
+CONFIG_INSTRUCTION_DECODER=y
+CONFIG_OUTPUT_FORMAT="elf64-x86-64"
+CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_MMU=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=28
+CONFIG_ARCH_MMAP_RND_BITS_MAX=32
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ZONE_DMA32=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_HAVE_INTEL_TXT=y
+CONFIG_X86_64_SMP=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION="-heads"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_KERNEL_XZ=y
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KERNEL_LZ4 is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_USELIB is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+# CONFIG_IRQ_DOMAIN_DEBUG is not set
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+# CONFIG_TASKS_RCU is not set
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_EXPEDITE_BOOT is not set
+CONFIG_BUILD_BIN2C=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_NMI_LOG_BUF_SHIFT=13
+CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+# CONFIG_CGROUPS is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../../../blobs/dev.cpio"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_RD_XZ=y
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_ANON_INODES=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_HAVE_PCSPKR_PLATFORM=y
+CONFIG_BPF=y
+CONFIG_EXPERT=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+# CONFIG_SYSFS_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_NMI=y
+CONFIG_BUG=y
+CONFIG_PCSPKR_PLATFORM=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_SHMEM=y
+# CONFIG_AIO is not set
+# CONFIG_ADVISE_SYSCALLS is not set
+# CONFIG_USERFAULTFD is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_MEMBARRIER is not set
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+CONFIG_SLUB_CPU_PARTIAL=y
+# CONFIG_SYSTEM_DATA_VERIFICATION is not set
+# CONFIG_PROFILING is not set
+CONFIG_KEXEC_CORE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_OPROFILE_NMI_TIMER=y
+# CONFIG_KPROBES is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+# CONFIG_UPROBES is not set
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_KPROBES_ON_FTRACE=y
+CONFIG_HAVE_NMI=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
+CONFIG_HAVE_USER_RETURN_NOTIFIER=y
+CONFIG_HAVE_PERF_EVENTS_NMI=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGINS is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR_NONE is not set
+# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
+CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_HAVE_ARCH_SOFT_DIRTY=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_ARCH_MMAP_RND_BITS=28
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_HAVE_STACK_VALIDATION=y
+# CONFIG_HAVE_ARCH_HASH is not set
+# CONFIG_ISA_BUS_API is not set
+# CONFIG_CPU_NO_EFFICIENT_FFS is not set
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+CONFIG_VMAP_STACK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_BLK_MQ_PCI=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_ASN1=m
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+# CONFIG_FREEZER is not set
+
+#
+# Processor type and features
+#
+CONFIG_ZONE_DMA=y
+CONFIG_SMP=y
+CONFIG_X86_FEATURE_NAMES=y
+CONFIG_X86_FAST_FEATURE_TESTS=y
+CONFIG_X86_MPPARSE=y
+# CONFIG_GOLDFISH is not set
+CONFIG_RETPOLINE=y
+# CONFIG_X86_EXTENDED_PLATFORM is not set
+# CONFIG_X86_INTEL_LPSS is not set
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+# CONFIG_IOSF_MBI is not set
+CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+# CONFIG_HYPERVISOR_GUEST is not set
+CONFIG_NO_BOOTMEM=y
+# CONFIG_MK8 is not set
+# CONFIG_MPSC is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MATOM is not set
+CONFIG_GENERIC_CPU=y
+CONFIG_X86_INTERNODE_CACHE_SHIFT=6
+CONFIG_X86_L1_CACHE_SHIFT=6
+CONFIG_X86_TSC=y
+CONFIG_X86_CMPXCHG64=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=64
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_CPU_SUP_INTEL=y
+CONFIG_CPU_SUP_AMD=y
+# CONFIG_CPU_SUP_CENTAUR is not set
+CONFIG_HPET_TIMER=y
+CONFIG_HPET_EMULATE_RTC=y
+CONFIG_DMI=y
+# CONFIG_GART_IOMMU is not set
+# CONFIG_CALGARY_IOMMU is not set
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+# CONFIG_MAXSMP is not set
+CONFIG_NR_CPUS=64
+# CONFIG_SCHED_SMT is not set
+CONFIG_SCHED_MC=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+CONFIG_X86_LOCAL_APIC=y
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_MCE=y
+CONFIG_X86_MCE_INTEL=y
+# CONFIG_X86_MCE_AMD is not set
+CONFIG_X86_MCE_THRESHOLD=y
+# CONFIG_X86_MCE_INJECT is not set
+CONFIG_X86_THERMAL_VECTOR=y
+
+#
+# Performance monitoring
+#
+CONFIG_PERF_EVENTS_INTEL_UNCORE=y
+# CONFIG_PERF_EVENTS_INTEL_RAPL is not set
+CONFIG_PERF_EVENTS_INTEL_CSTATE=y
+# CONFIG_PERF_EVENTS_AMD_POWER is not set
+# CONFIG_VM86 is not set
+CONFIG_X86_VSYSCALL_EMULATION=y
+# CONFIG_I8K is not set
+# CONFIG_MICROCODE is not set
+# CONFIG_X86_MSR is not set
+# CONFIG_X86_CPUID is not set
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_X86_DIRECT_GBPAGES=y
+# CONFIG_NUMA is not set
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
+# CONFIG_SPARSEMEM_VMEMMAP is not set
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+# CONFIG_COMPACTION is not set
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_BOUNCE is not set
+CONFIG_VIRT_TO_BUS=y
+CONFIG_MMU_NOTIFIER=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+# CONFIG_MEMORY_FAILURE is not set
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+# CONFIG_CLEANCACHE is not set
+# CONFIG_CMA is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_X86_PMEM_LEGACY_DEVICE=y
+CONFIG_X86_PMEM_LEGACY=y
+# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
+CONFIG_X86_RESERVE_LOW=64
+# CONFIG_MTRR is not set
+CONFIG_ARCH_RANDOM=y
+# CONFIG_X86_SMAP is not set
+# CONFIG_X86_INTEL_MPX is not set
+# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
+# CONFIG_EFI is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+# CONFIG_KEXEC_VERIFY_SIG is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_PHYSICAL_START=0x1000000
+# CONFIG_RELOCATABLE is not set
+CONFIG_PHYSICAL_ALIGN=0x1000000
+# CONFIG_HOTPLUG_CPU is not set
+# CONFIG_LEGACY_VSYSCALL_NATIVE is not set
+CONFIG_LEGACY_VSYSCALL_EMULATE=y
+# CONFIG_LEGACY_VSYSCALL_NONE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_MODIFY_LDT_SYSCALL is not set
+CONFIG_HAVE_LIVEPATCH=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+
+#
+# Power management and ACPI options
+#
+# CONFIG_SUSPEND is not set
+# CONFIG_PM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_PROCFS_POWER is not set
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_VIDEO=y
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_DOCK is not set
+CONFIG_ACPI_CPU_FREQ_PSS=y
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_PROCESSOR=y
+# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_CUSTOM_DSDT_FILE=""
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_X86_PM_TIMER=y
+# CONFIG_ACPI_CONTAINER is not set
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_SBS is not set
+# CONFIG_ACPI_HED is not set
+# CONFIG_ACPI_CUSTOM_METHOD is not set
+# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
+# CONFIG_ACPI_NFIT is not set
+CONFIG_HAVE_ACPI_APEI=y
+CONFIG_HAVE_ACPI_APEI_NMI=y
+# CONFIG_ACPI_APEI is not set
+# CONFIG_DPTF_POWER is not set
+# CONFIG_ACPI_EXTLOG is not set
+# CONFIG_PMIC_OPREGION is not set
+# CONFIG_ACPI_CONFIGFS is not set
+# CONFIG_SFI is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+# CONFIG_INTEL_IDLE is not set
+
+#
+# Memory power savings
+#
+# CONFIG_I7300_IDLE is not set
+
+#
+# Bus options (PCI etc.)
+#
+CONFIG_PCI=y
+CONFIG_PCI_DIRECT=y
+# CONFIG_PCI_MMCONFIG is not set
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_CNB20LE_QUIRK is not set
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_PCI_BUS_ADDR_T_64BIT=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_HT_IRQ is not set
+CONFIG_PCI_ATS=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_LABEL=y
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# PCI host controller drivers
+#
+# CONFIG_PCIE_DW_PLAT is not set
+# CONFIG_VMD is not set
+# CONFIG_ISA_BUS is not set
+CONFIG_ISA_DMA_API=y
+CONFIG_AMD_NB=y
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+# CONFIG_X86_SYSFB is not set
+
+#
+# Executable file formats / Emulations
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_COREDUMP is not set
+# CONFIG_IA32_EMULATION is not set
+# CONFIG_X86_X32 is not set
+CONFIG_X86_DEV_DMA_OPS=y
+CONFIG_PMC_ATOM=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+# CONFIG_UNIX is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IP_TUNNEL is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_NET_UDP_TUNNEL is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NET_PTP_CLASSIFY=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_MPLS is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_SOCK_CGROUP_DATA is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_STREAM_PARSER is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_LWTUNNEL is not set
+# CONFIG_DST_CACHE is not set
+# CONFIG_NET_DEVLINK is not set
+CONFIG_MAY_USE_DEVLINK=y
+CONFIG_HAVE_EBPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_FENCE_TRACE is not set
+
+#
+# Bus devices
+#
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_OF is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+
+#
+# Protocols
+#
+CONFIG_PNPACPI=y
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SKD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+# CONFIG_BLK_DEV_NVME is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_IBM_ASM is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_SRAM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_INTEL_MEI=m
+CONFIG_INTEL_MEI_ME=m
+CONFIG_INTEL_MEI_TXE=m
+# CONFIG_VMWARE_VMCI is not set
+
+#
+# Intel MIC Bus Driver
+#
+# CONFIG_INTEL_MIC_BUS is not set
+
+#
+# SCIF Bus Driver
+#
+# CONFIG_SCIF_BUS is not set
+
+#
+# VOP Bus Driver
+#
+# CONFIG_VOP_BUS is not set
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+
+#
+# SCIF Driver
+#
+
+#
+# Intel MIC Coprocessor State Management (COSM) Drivers
+#
+
+#
+# VOP Driver
+#
+# CONFIG_GENWQE is not set
+# CONFIG_ECHO is not set
+# CONFIG_CXL_BASE is not set
+# CONFIG_CXL_AFU_DRIVER_OPS is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_MQ_DEFAULT is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=y
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=y
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_MVUMI is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_SCSI_ESAS2R is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT3SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_SMARTPQI is not set
+# CONFIG_SCSI_UFSHCD is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_VMWARE_PVSCSI is not set
+# CONFIG_SCSI_SNIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_ISCI is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_ACPI=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_ATA_SFF is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BCACHE is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_MQ_DEFAULT is not set
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_BUFIO=y
+# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set
+CONFIG_DM_CRYPT=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+CONFIG_DM_VERITY=y
+CONFIG_DM_VERITY_FEC=y
+# CONFIG_DM_SWITCH is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+# CONFIG_VETH is not set
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_CX_ECAT is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_NET_VENDOR_INTEL=y
+# CONFIG_E100 is not set
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_E1000E_HWTS=y
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGBEVF is not set
+# CONFIG_I40E is not set
+# CONFIG_I40EVF is not set
+# CONFIG_FM10K is not set
+# CONFIG_NET_VENDOR_I825XX is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_NET_SB1000 is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_FUJITSU_ES is not set
+# CONFIG_ISDN is not set
+# CONFIG_NVM is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_USERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+# CONFIG_SERIAL_8250_PNP is not set
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_FSL is not set
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_LPSS is not set
+# CONFIG_SERIAL_8250_MID is not set
+# CONFIG_SERIAL_8250_MOXA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+CONFIG_TTY_PRINTK=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_HW_RANDOM_INTEL=m
+CONFIG_HW_RANDOM_AMD=m
+CONFIG_HW_RANDOM_VIA=m
+CONFIG_HW_RANDOM_TPM=m
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_MWAVE is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_HPET is not set
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_CORE=y
+CONFIG_TCG_TIS=y
+# CONFIG_TCG_TIS_I2C_ATMEL is not set
+# CONFIG_TCG_TIS_I2C_INFINEON is not set
+# CONFIG_TCG_TIS_I2C_NUVOTON is not set
+# CONFIG_TCG_NSC is not set
+# CONFIG_TCG_ATMEL is not set
+# CONFIG_TCG_INFINEON is not set
+# CONFIG_TCG_CRB is not set
+# CONFIG_TCG_VTPM_PROXY is not set
+# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
+# CONFIG_TELCLOCK is not set
+CONFIG_DEVPORT=y
+# CONFIG_XILLYBUS is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_MUX=m
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_REG=m
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_ISMT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# ACPI drivers
+#
+# CONFIG_I2C_SCMI is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_EEPROM is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_SPI is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_POWER_RESET is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_WRITABLE_TRIPS is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+# CONFIG_THERMAL_GOV_BANG_BANG is not set
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
+# CONFIG_THERMAL_EMULATION is not set
+# CONFIG_INTEL_POWERCLAMP is not set
+# CONFIG_X86_PKG_TEMP_THERMAL is not set
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+
+#
+# ACPI INT340X thermal drivers
+#
+# CONFIG_INT340X_THERMAL is not set
+# CONFIG_INTEL_PCH_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_EXYNOS_LPASS is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_INTEL_LPSS_ACPI is not set
+# CONFIG_MFD_INTEL_LPSS_PCI is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RTSX_PCI is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RTSX_USB is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_ABX500_CORE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_VGA_SWITCHEROO is not set
+CONFIG_DRM=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_AMDGPU is not set
+
+#
+# ACP (Audio CoProcessor) Configuration
+#
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_I915 is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VMWGFX is not set
+# CONFIG_DRM_GMA500 is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_QXL is not set
+# CONFIG_DRM_BOCHS is not set
+CONFIG_DRM_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_LEGACY is not set
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_BOOT_VESA_SUPPORT=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+CONFIG_FB_VESA=y
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SM712 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_APPLE is not set
+# CONFIG_BACKLIGHT_PM8941_WLED is not set
+# CONFIG_BACKLIGHT_SAHARA is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_VGASTATE is not set
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_LOGO is not set
+# CONFIG_SOUND is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+
+#
+# Intel ISH HID support
+#
+# CONFIG_INTEL_ISH_HID is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_PCI=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_UCSI is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_USB_PHY is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_USB_ULPI_BUS is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8010 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV8803 is not set
+
+#
+# SPI RTC drivers
+#
+CONFIG_RTC_I2C_AND_SPI=y
+
+#
+# SPI and I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_PCF2127 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# Platform RTC drivers
+#
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# DMABUF options
+#
+# CONFIG_SYNC_FILE is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VFIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_STAGING is not set
+# CONFIG_X86_PLATFORM_DEVICES is not set
+# CONFIG_CHROME_PLATFORMS is not set
+
+#
+# Hardware Spinlock drivers
+#
+
+#
+# Clock Source drivers
+#
+CONFIG_CLKEVT_I8253=y
+CONFIG_I8253_LOCK=y
+CONFIG_CLKBLD_I8253=y
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+# CONFIG_MAILBOX is not set
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IOVA=y
+# CONFIG_AMD_IOMMU is not set
+CONFIG_DMAR_TABLE=y
+CONFIG_INTEL_IOMMU=y
+CONFIG_INTEL_IOMMU_SVM=y
+CONFIG_INTEL_IOMMU_DEFAULT_ON=y
+CONFIG_INTEL_IOMMU_FLOPPY_WA=y
+# CONFIG_IRQ_REMAP is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Broadcom SoC drivers
+#
+# CONFIG_SUNXI_SRAM is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_NTB is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+CONFIG_ARM_GIC_MAX_NR=1
+# CONFIG_IPACK_BUS is not set
+# CONFIG_RESET_CONTROLLER is not set
+# CONFIG_FMC is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+# CONFIG_RAS is not set
+# CONFIG_THUNDERBOLT is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+CONFIG_LIBNVDIMM=y
+# CONFIG_BLK_DEV_PMEM is not set
+# CONFIG_ND_BLK is not set
+# CONFIG_BTT is not set
+# CONFIG_NVMEM is not set
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+
+#
+# FPGA Configuration Support
+#
+# CONFIG_FPGA is not set
+
+#
+# Firmware Drivers
+#
+# CONFIG_EDD is not set
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_DELL_RBU is not set
+# CONFIG_DCDBAS is not set
+# CONFIG_DMIID is not set
+# CONFIG_DMI_SYSFS is not set
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+# CONFIG_ISCSI_IBFT_FIND is not set
+# CONFIG_FW_CFG_SYSFS is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_ENCRYPTION is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_FS_DAX is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+# CONFIG_PROC_SYSCTL is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_DYNAMIC_DEBUG=y
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+# CONFIG_DEBUG_INFO_SPLIT is not set
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_GDB_SCRIPTS=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+CONFIG_UNUSED_SYMBOLS=y
+# CONFIG_PAGE_OWNER is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+CONFIG_STACK_VALIDATION=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_DEBUG_KERNEL=y
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VIRTUAL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+CONFIG_HAVE_ARCH_KMEMCHECK=y
+CONFIG_ARCH_HAS_KCOV=y
+# CONFIG_KCOV is not set
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_HARDLOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+# CONFIG_TIMER_STATS is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PI_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_PROVE_RCU is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_TORTURE_TEST is not set
+# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_FENTRY=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+
+#
+# Runtime Testing
+#
+# CONFIG_LKDTM is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_MEMTEST is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
+# CONFIG_UBSAN is not set
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+# CONFIG_STRICT_DEVMEM is not set
+# CONFIG_X86_VERBOSE_BOOTUP is not set
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EARLY_PRINTK_DBGP is not set
+# CONFIG_X86_PTDUMP_CORE is not set
+# CONFIG_X86_PTDUMP is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+# CONFIG_DEBUG_WX is not set
+CONFIG_DEBUG_SET_MODULE_RONX=y
+# CONFIG_DEBUG_NX_TEST is not set
+# CONFIG_DOUBLEFAULT is not set
+# CONFIG_DEBUG_TLBFLUSH is not set
+# CONFIG_IOMMU_STRESS is not set
+CONFIG_HAVE_MMIOTRACE_SUPPORT=y
+CONFIG_IO_DELAY_TYPE_0X80=0
+CONFIG_IO_DELAY_TYPE_0XED=1
+CONFIG_IO_DELAY_TYPE_UDELAY=2
+CONFIG_IO_DELAY_TYPE_NONE=3
+# CONFIG_IO_DELAY_0X80 is not set
+CONFIG_IO_DELAY_0XED=y
+# CONFIG_IO_DELAY_UDELAY is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_DEFAULT_IO_DELAY_TYPE=1
+# CONFIG_DEBUG_BOOT_PARAMS is not set
+# CONFIG_CPA_DEBUG is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_DEBUG_ENTRY is not set
+# CONFIG_DEBUG_NMI_SELFTEST is not set
+# CONFIG_X86_DEBUG_FPU is not set
+# CONFIG_PUNIT_ATOM_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_PAGE_TABLE_ISOLATION=y
+CONFIG_SECURITYFS=y
+# CONFIG_INTEL_TXT is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
+CONFIG_HARDENED_USERCOPY=y
+# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=m
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=m
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_RSA=m
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_ECDH is not set
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_MCRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_ABLK_HELPER=y
+CONFIG_CRYPTO_GLUE_HELPER_X86=y
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_ECHAINIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_KEYWRAP=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32C_INTEL=y
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRC32_PCLMUL=m
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_POLY1305_X86_64=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_SSSE3=y
+# CONFIG_CRYPTO_SHA256_SSSE3 is not set
+# CONFIG_CRYPTO_SHA512_SSSE3 is not set
+# CONFIG_CRYPTO_SHA1_MB is not set
+# CONFIG_CRYPTO_SHA256_MB is not set
+# CONFIG_CRYPTO_SHA512_MB is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_AES_X86_64=y
+CONFIG_CRYPTO_AES_NI_INTEL=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH_X86_64=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAMELLIA_X86_64=m
+CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m
+CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST5_AVX_X86_64=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST6_AVX_X86_64=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_DES3_EDE_X86_64=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SALSA20_X86_64=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20_X86_64=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m
+CONFIG_CRYPTO_SERPENT_AVX_X86_64=m
+CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH_X86_64=m
+CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m
+CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_842=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_DRBG_MENU=m
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG=m
+CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+CONFIG_CRYPTO_USER_API_AEAD=y
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_HAVE_KVM=y
+# CONFIG_VIRTUALIZATION is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_842_COMPRESS=m
+CONFIG_842_DECOMPRESS=m
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=m
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_TEST=m
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+CONFIG_CLZ_TAB=y
+CONFIG_CORDIC=m
+# CONFIG_DDR is not set
+CONFIG_IRQ_POLL=y
+CONFIG_MPILIB=m
+CONFIG_FONT_SUPPORT=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_SG_SPLIT is not set
+CONFIG_SG_POOL=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_PMEM_API=y
+CONFIG_ARCH_HAS_MMIO_FLUSH=y
+CONFIG_SBITMAP=y
diff --git a/initrd/bin/flashrom-kgpe-d16-openbmc.sh b/initrd/bin/flashrom-kgpe-d16-openbmc.sh
new file mode 100755
index 00000000..138ce035
--- /dev/null
+++ b/initrd/bin/flashrom-kgpe-d16-openbmc.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+. /etc/functions
+
+ROM="$1"
+if [ -z "$1" ]; then
+	die "Usage: $0 /media/kgpe-d16-openbmc.rom"
+fi
+
+cp "$ROM" /tmp/kgpe-d16-openbmc.rom
+sha256sum /tmp/kgpe-d16-openbmc.rom
+
+flashrom --programmer="ast1100:spibus=2,cpu=reset" -c "S25FL128P......0" -w /tmp/kgpe-d16-openbmc.rom \
+|| die "$ROM: Flash failed"
+
+warn "Reboot and hopefully it works..."
+exit 0
diff --git a/initrd/bin/flashrom-kgpe-d16.sh b/initrd/bin/flashrom-kgpe-d16.sh
new file mode 100755
index 00000000..135c4b6c
--- /dev/null
+++ b/initrd/bin/flashrom-kgpe-d16.sh
@@ -0,0 +1,20 @@
+#!/bin/sh
+. /etc/functions
+
+ROM="$1"
+if [ -z "$1" ]; then
+	die "Usage: $0 /media/kgpe-d16.rom"
+fi
+
+cp "$ROM" /tmp/kgpe-d16.rom
+sha256sum /tmp/kgpe-d16.rom
+
+flashrom \
+	--force \
+	--noverify \
+	--programmer internal \
+	-w /tmp/kgpe-d16.rom \
+|| die "$ROM: Flash failed"
+
+warn "Reboot and hopefully it works..."
+exit 0
diff --git a/initrd/etc/motd b/initrd/etc/motd
deleted file mode 100644
index c7748bb7..00000000
--- a/initrd/etc/motd
+++ /dev/null
@@ -1,6 +0,0 @@
- _   _                _          __  _   _ _____ ____  _____ 
-| | | | ___  __ _  __| |___     / / | \ | | ____|  _ \|  ___|
-| |_| |/ _ \/ _` |/ _` / __|   / /  |  \| |  _| | |_) | |_   
-|  _  |  __/ (_| | (_| \__ \  / /   | |\  | |___|  _ <|  _|  
-|_| |_|\___|\__,_|\__,_|___/ /_/    |_| \_|_____|_| \_\_|    
-                                                             
diff --git a/patches/coreboot-4.7.patch b/patches/coreboot-4.7.patch
index b386af7d..f823e8ff 100644
--- a/patches/coreboot-4.7.patch
+++ b/patches/coreboot-4.7.patch
@@ -24,6 +24,59 @@ index 6896d0e..577bd52 100644
  endmenu
  
  menu "Mainboard"
+diff --git ./src/drivers/pc80/tpm/romstage.c ./src/drivers/pc80/tpm/romstage.c
+index 5531458..95e65f2 100644
+--- ./src/drivers/pc80/tpm/romstage.c
++++ ./src/drivers/pc80/tpm/romstage.c
+@@ -48,6 +48,12 @@ static const struct {
+ 
+ static const struct {
+ 	u8 buffer[12];
++} tpm2_startup_cmd = {
++	{0x80, 0x01, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x01, 0x44, 0x0, 0x0 }
++};
++
++static const struct {
++	u8 buffer[12];
+ } tpm_deactivate_cmd = {
+ 	{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x3 }
+ };
+@@ -229,9 +235,15 @@ void init_tpm(int s3resume)
+ 			return;
+ 		}
+ 	} else {
+-		printk(BIOS_SPEW, "TPM: Startup\n");
+-		result = TlclSendReceive(tpm_startup_cmd.buffer,
+-					response, sizeof(response));
++		if (IS_ENABLED(CONFIG_TPM2)) {
++			printk(BIOS_SPEW, "TPM2: Startup\n");
++			result = TlclSendReceive(tpm2_startup_cmd.buffer,
++						response, sizeof(response));
++		} else {
++			printk(BIOS_SPEW, "TPM: Startup\n");
++			result = TlclSendReceive(tpm_startup_cmd.buffer,
++						response, sizeof(response));
++		}
+ 	}
+ 
+ 	tis_close();
+diff --git ./src/drivers/pc80/tpm/tpm.c ./src/drivers/pc80/tpm/tpm.c
+index 574d3af..9bdc73f 100644
+--- ./src/drivers/pc80/tpm/tpm.c
++++ ./src/drivers/pc80/tpm/tpm.c
+@@ -125,10 +125,11 @@ static const struct device_name atmel_devices[] = {
+ 
+ static const struct device_name infineon_devices[] = {
+ 	{0x000b, "SLB9635 TT 1.2"},
+-	{0x001a, "SLB9660 TT 1.2"},
+ #if IS_ENABLED(CONFIG_TPM2)
++	{0x001a, "SLB9665 TT 2.0"},
+ 	{0x001b, "SLB9670 TT 2.0"},
+ #else
++	{0x001a, "SLB9660 TT 1.2"},
+ 	{0x001b, "SLB9670 TT 1.2"},
+ #endif
+ 	{0xffff}
 diff --git ./src/include/program_loading.h ./src/include/program_loading.h
 index 416e2e9..40486cd 100644
 --- ./src/include/program_loading.h
@@ -420,6 +473,158 @@ index 49854cb..32eb128 100644
 +	return tlcl_extend(pcr_num, hash, NULL);
 +}
 +
+diff --git ./src/mainboard/asus/kgpe-d16/Kconfig ./src/mainboard/asus/kgpe-d16/Kconfig
+index 531ba4f..5227d28 100644
+--- ./src/mainboard/asus/kgpe-d16/Kconfig
++++ ./src/mainboard/asus/kgpe-d16/Kconfig
+@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+ 	select BOARD_ROMSIZE_KB_2048
+ 	select ENABLE_APIC_EXT_ID
+ 	select SPI_FLASH
++	select TPM2
+ 	select MAINBOARD_HAS_LPC_TPM
+ 	select HAVE_ACPI_RESUME
+ 	select DRIVERS_I2C_W83795
+diff --git ./src/mainboard/asus/kgpe-d16/devicetree.cb ./src/mainboard/asus/kgpe-d16/devicetree.cb
+index 9039f6d..0ea4216 100644
+--- ./src/mainboard/asus/kgpe-d16/devicetree.cb
++++ ./src/mainboard/asus/kgpe-d16/devicetree.cb
+@@ -217,6 +217,9 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
+ 						chip drivers/pc80/tpm
+ 							device pnp 4e.0 on end		# TPM module
+ 						end
++						chip drivers/generic/generic		# BMC KCS
++							device pnp ca2.0 on end
++						end
+ 					end
+ 					device pci 14.4 on			# Bridge
+ 						device pci 1.0 on end		# VGA
+diff --git ./src/mainboard/asus/kgpe-d16/dsdt.asl ./src/mainboard/asus/kgpe-d16/dsdt.asl
+index 6a25b4d..cfcbc98 100644
+--- ./src/mainboard/asus/kgpe-d16/dsdt.asl
++++ ./src/mainboard/asus/kgpe-d16/dsdt.asl
+@@ -50,6 +50,9 @@ DefinitionBlock (
+ 	/* HPET enable */
+ 	Name (HPTE, 0x1)
+ 
++	/* IPMI KCS enable */
++	Name (KCSE, 0x1)
++
+ 	#include <southbridge/amd/common/acpi/sleepstates.asl>
+ 
+ 	/* The _PIC method is called by the OS to choose between interrupt
+@@ -485,6 +488,13 @@ DefinitionBlock (
+ 				Name (_HID, EisaId ("PNP0A05"))
+ 				Name (_ADR, 0x00140003)
+ 
++				OperationRegion(BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */
++					Field(BMRG, AnyAcc, NoLock, Preserve)
++				{
++					BMRI, 8,  /* Index */
++					BMRD, 8,  /* Data */
++				}
++
+ 				/* Real Time Clock Device */
+ 				Device(RTC0) {
+ 					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
+@@ -606,6 +616,27 @@ DefinitionBlock (
+ 						})
+ 					}
+ 				}
++
++				Device(KCS1) {   /* IPMI KCS */
++					Name(_HID,EISAID("IPI0001"))		/* ASpeed BMC */
++					Method (_STA, 0, NotSerialized) {
++						If(KCSE) {			/* Detection enabled */
++							If(LNotEqual(BMRD, 0xff)) {
++								Return(0x0f)	/* Device present */
++							}
++							Return(Zero)
++						}
++						Return(Zero)
++					}
++					Method(_CRS, 0) {
++						Return(ResourceTemplate() {
++							IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02)
++						})
++					}
++					Method (_IFT, 0, NotSerialized) {	/* Interface type */
++						Return(One)			/* KCS interface */
++					}
++				}
+ 			}
+ 
+ 			/* High Precision Event Timer */
+diff --git ./src/mainboard/asus/kgpe-d16/mainboard.c ./src/mainboard/asus/kgpe-d16/mainboard.c
+index 65029d4..8ee3a5e 100644
+--- ./src/mainboard/asus/kgpe-d16/mainboard.c
++++ ./src/mainboard/asus/kgpe-d16/mainboard.c
+@@ -70,6 +70,13 @@ static void mainboard_enable(device_t dev)
+ 
+ 	set_pcie_dereset();
+ 	/* get_ide_dma66(); */
++
++	/* Enable access to the BMC IPMI via KCS */
++	device_t lpc_sio_dev = dev_find_slot_pnp(0xca2, 0);
++	struct resource *res = new_resource(lpc_sio_dev, 0xca2);
++	res->base = 0xca2;
++	res->size = 1;
++	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+ 
+ /* override the default SATA PHY setup */
+diff --git ./src/mainboard/asus/kgpe-d16/romstage.c ./src/mainboard/asus/kgpe-d16/romstage.c
+index 63b93c1..bb4f181 100644
+--- ./src/mainboard/asus/kgpe-d16/romstage.c
++++ ./src/mainboard/asus/kgpe-d16/romstage.c
+@@ -88,6 +88,47 @@ static void switch_spd_mux(uint8_t channel)
+ 	byte &= ~0xc0;			/* Enable SPD mux GPIO output drivers */
+ 	byte |= (channel << 2) & 0xc;	/* Set SPD mux GPIOs */
+ 	pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
++
++	/* Temporary AST PCI mapping */
++	uint32_t base_memory = 0xfc000000;
++	uint32_t memory_limit = 0xfc800000;
++
++	/* Temporarily enable the SP5100 PCI bridge */
++	uint16_t prev_sec_cfg = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x04);
++	uint8_t prev_sec_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x19);
++	uint8_t prev_sec_sub_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x1a);
++	uint16_t prev_sec_mem_base = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x20);
++	uint16_t prev_sec_mem_limit = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x22);
++	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, 0x01);
++	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, 0xff);
++	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, (base_memory >> 20));
++	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, (memory_limit >> 20));
++	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, 0x2);
++
++	/* Temporarily enable AST BAR1 */
++	uint32_t prev_ast_cfg = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x04);
++	uint32_t prev_ast_bar1 = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x14);
++	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, base_memory);
++	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, 0x02100002);
++
++	/* Use the P2A bridge to set ASpeed SPD mux GPIOs to the same values as the SP5100 */
++	void* ast_bar1 = (void*)base_memory;
++	write32(ast_bar1 + 0xf004, 0x1e780000);								/* Enable access to GPIO controller */
++	write32(ast_bar1 + 0xf000, 0x1);
++	write32(ast_bar1 + 0x10024, read32(ast_bar1 + 0x10024) | 0x3000);				/* Enable SPD mux GPIO output drivers */
++	write32(ast_bar1 + 0x10020, (read32(ast_bar1 + 0x10020) & ~0x3000) | ((channel & 0x3) << 12));	/* Set SPD mux GPIOs */
++	write32(ast_bar1 + 0xf000, 0x0);
++
++	/* Deconfigure AST BAR1 */
++	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, prev_ast_cfg);
++	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, prev_ast_bar1);
++
++	/* Deconfigure SP5100 PCI bridge */
++	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, prev_sec_cfg);
++	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, prev_sec_mem_limit);
++	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, prev_sec_mem_base);
++	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, prev_sec_sub_bus);
++	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, prev_sec_bus);
+ }
+ 
+ static const uint8_t spd_addr_fam15[] = {
 diff --git ./src/northbridge/intel/sandybridge/romstage.c ./src/northbridge/intel/sandybridge/romstage.c
 index 8608d5a..dac90ee 100644
 --- ./src/northbridge/intel/sandybridge/romstage.c
diff --git a/patches/flashrom-0.9.9.patch b/patches/flashrom-0.9.9.patch
index 86ccda66..4765465e 100644
--- a/patches/flashrom-0.9.9.patch
+++ b/patches/flashrom-0.9.9.patch
@@ -1,7 +1,1519 @@
-diff -u -x '*.d' -x '*.o' ../clean/flashrom-0.9.9/spi.c flashrom-0.9.9/spi.c
---- ../clean/flashrom-0.9.9/spi.c	2014-07-20 00:03:29.000000000 +0200
-+++ flashrom-0.9.9/spi.c	2017-04-19 00:04:25.138374544 +0200
-@@ -100,6 +100,20 @@
+diff --git ./Makefile ./Makefile
+index 4ebde1e..4257e82 100644
+--- ./Makefile
++++ ./Makefile
+@@ -214,6 +214,16 @@ UNSUPPORTED_FEATURES += CONFIG_GFXNVIDIA=yes
+ else
+ override CONFIG_GFXNVIDIA = no
+ endif
++ifeq ($(CONFIG_AST1100), yes)
++UNSUPPORTED_FEATURES += CONFIG_AST1100=yes
++else
++override CONFIG_AST1100 = no
++endif
++ifeq ($(CONFIG_AST2400), yes)
++UNSUPPORTED_FEATURES += CONFIG_AST2400=yes
++else
++override CONFIG_AST2400 = no
++endif
+ ifeq ($(CONFIG_SATASII), yes)
+ UNSUPPORTED_FEATURES += CONFIG_SATASII=yes
+ else
+@@ -441,6 +451,16 @@ UNSUPPORTED_FEATURES += CONFIG_GFXNVIDIA=yes
+ else
+ override CONFIG_GFXNVIDIA = no
+ endif
++ifeq ($(CONFIG_AST1100), yes)
++UNSUPPORTED_FEATURES += CONFIG_AST1100=yes
++else
++override CONFIG_AST1100 = no
++endif
++ifeq ($(CONFIG_AST2400), yes)
++UNSUPPORTED_FEATURES += CONFIG_AST2400=yes
++else
++override CONFIG_AST2400 = no
++endif
+ ifeq ($(CONFIG_SATASII), yes)
+ UNSUPPORTED_FEATURES += CONFIG_SATASII=yes
+ else
+@@ -514,7 +534,7 @@ endif
+ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \
+ 	sst28sf040.o 82802ab.o \
+ 	sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \
+-	opaque.o sfdp.o en29lv640b.o at45db.o
++	spi4ba.o opaque.o sfdp.o en29lv640b.o at45db.o
+ 
+ ###############################################################################
+ # Library code.
+@@ -565,6 +585,12 @@ CONFIG_NIC3COM ?= yes
+ # Enable NVIDIA graphics cards. Note: write and erase do not work properly.
+ CONFIG_GFXNVIDIA ?= yes
+ 
++# Enable AST1100 BMC SoCs.
++CONFIG_AST1100 ?= yes
++
++# Enable AST2400 BMC SoCs.
++CONFIG_AST2400 ?= yes
++
+ # Always enable SiI SATA controllers for now.
+ CONFIG_SATASII ?= yes
+ 
+@@ -664,6 +690,8 @@ ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no)
+ override CONFIG_INTERNAL = no
+ override CONFIG_NIC3COM = no
+ override CONFIG_GFXNVIDIA = no
++override CONFIG_AST1100 = no
++override CONFIG_AST2400 = no
+ override CONFIG_SATASII = no
+ override CONFIG_ATAHPT = no
+ override CONFIG_ATAVIA = no
+@@ -776,6 +804,18 @@ PROGRAMMER_OBJS += gfxnvidia.o
+ NEED_LIBPCI += CONFIG_GFXNVIDIA
+ endif
+ 
++ifeq ($(CONFIG_AST1100), yes)
++FEATURE_CFLAGS += -D'CONFIG_AST1100=1'
++PROGRAMMER_OBJS += ast1100.o
++NEED_LIBPCI += CONFIG_AST1100
++endif
++
++ifeq ($(CONFIG_AST2400), yes)
++FEATURE_CFLAGS += -D'CONFIG_AST2400=1'
++PROGRAMMER_OBJS += ast2400.o
++NEED_LIBPCI += CONFIG_AST2400
++endif
++
+ ifeq ($(CONFIG_SATASII), yes)
+ FEATURE_CFLAGS += -D'CONFIG_SATASII=1'
+ PROGRAMMER_OBJS += satasii.o
+diff --git ./ast1100.c ./ast1100.c
+new file mode 100644
+index 0000000..f661271
+--- /dev/null
++++ ./ast1100.c
+@@ -0,0 +1,421 @@
++/*
++ * This file is part of the flashrom project.
++ *
++ * Copyright (C) 2017 Raptor Engineering, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
++ */
++
++#include <stdlib.h>
++#include <string.h>
++#include "flash.h"
++#include "programmer.h"
++#include "hwaccess.h"
++
++#define PCI_VENDOR_ID_ASPEED		0x1a03
++
++#define ASPEED_MEMMAP_SIZE		(128 * 1024)
++#define ASPEED_P2A_OFFSET		0x10000
++
++#define AST1100_SCU_APB_ADDR		0x1e6e2000
++#define AST1100_SCU_APB_BRIDGE_OFFSET	(AST1100_SCU_APB_ADDR & 0xffff)
++#define AST1100_SCU_PROT_KEY		0x00
++#define AST1100_SCU_HW_STRAP		0x70
++
++#define AST1100_SCU_PASSWORD		0x1688a8a8
++#define AST1100_SCU_BOOT_SRC_MASK	0x3
++#define AST1100_SCU_BOOT_SPI		0x2
++#define AST1100_SCU_BOOT_NONE		0x3
++
++#define AST1100_SMC_APB_ADDR		0x16000000
++#define AST1100_SMC_SMC00		0x00
++#define AST1100_SMC_CE_CTL(N)		(0x4 + (N * 4))
++
++#define AST1100_SMC_SEGMENT_SIZE_MASK	0x3
++#define AST1100_SMC_SEGMENT_SIZE_32M	0x0
++#define AST1100_SMC_SEGMENT_SIZE_16M	0x1
++#define AST1100_SMC_SEGMENT_SIZE_8M	0x2
++#define AST1100_SMC_SEGMENT_SIZE_4M	0x3
++
++#define AST1100_SMC_FLASH_MMIO_ADDR	0x10000000
++
++#define AST1100_SPI_CMD_FAST_R_MODE	0x1
++#define AST1100_SPI_CMD_USER_MODE	0x3
++#define AST1100_SPI_CMD_MASK		0x3
++#define AST1100_SPI_STOP_CE_ACTIVE	(0x1 << 2)
++#define AST1100_SPI_SPEED_SHIFT		8
++#define AST1100_SPI_SPEED_MASK		(0x7 << AST1100_SPI_SPEED_SHIFT)
++
++#define AST1100_SPI_FLASH_MMIO_ADDR	0x30000000
++
++#define AST1100_WDT_APB_ADDR		0x1e785000
++#define AST1100_WDT_APB_BRIDGE_OFFSET	(AST1100_WDT_APB_ADDR & 0xffff)
++
++#define AST1100_WDT1_CTR		0x00
++#define AST1100_WDT1_CTR_RELOAD		0x04
++#define AST1100_WDT1_CTR_RESTART	0x08
++#define AST1100_WDT1_CTL		0x0c
++
++#define AST1100_WDT_SET_CLOCK		(0x1 << 4)
++#define AST1100_WDT_RESET_SYSTEM	(0x1 << 1)
++#define AST1100_WDT_ENABLE		(0x1 << 0)
++
++uint8_t *ast1100_device_bar = 0;
++uint8_t ast1100_device_spi_bus = 0;
++uint8_t ast1100_device_spi_speed = 0;
++uint8_t ast1100_device_halt_cpu = 0;
++uint8_t ast1100_device_reset_cpu = 0;
++uint8_t ast1100_device_resume_cpu = 0;
++uint8_t ast1100_device_tickle_fw = 0;
++uint32_t ast1100_device_flash_mmio_offset = 0;
++uint32_t ast1100_original_wdt_conf = 0;
++
++const struct dev_entry bmc_aspeed_ast1100[] = {
++	{PCI_VENDOR_ID_ASPEED, 0x2000, OK, "ASPEED", "AST1100" },
++
++	{0},
++};
++
++static int ast1100_spi_send_command(struct flashctx *flash,
++				   unsigned int writecnt, unsigned int readcnt,
++				   const unsigned char *writearr,
++				   unsigned char *readarr);
++
++static const struct spi_master spi_master_ast1100 = {
++	.type		= SPI_CONTROLLER_AST1100,
++	.max_data_read	= 256,
++	.max_data_write	= 256,
++	.command	= ast1100_spi_send_command,
++	.multicommand	= default_spi_send_multicommand,
++	.read		= default_spi_read,
++	.write_256	= default_spi_write_256,
++	.write_aai	= default_spi_write_aai,
++};
++
++static int ast1100_set_a2b_bridge_scu(void)
++{
++	pci_mmio_writel(0x0, ast1100_device_bar + 0xf000);
++	pci_mmio_writel(AST1100_SCU_APB_ADDR & 0xffff0000, ast1100_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast1100_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast1100_set_a2b_bridge_wdt(void)
++{
++	pci_mmio_writel(0x0, ast1100_device_bar + 0xf000);
++	pci_mmio_writel(AST1100_WDT_APB_ADDR & 0xffff0000, ast1100_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast1100_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast1100_set_a2b_bridge_smc(void)
++{
++	pci_mmio_writel(0x0, ast1100_device_bar + 0xf000);
++	pci_mmio_writel(AST1100_SMC_APB_ADDR, ast1100_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast1100_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast1100_set_a2b_bridge_smc_flash(void)
++{
++	pci_mmio_writel(0x0, ast1100_device_bar + 0xf000);
++	pci_mmio_writel(AST1100_SMC_FLASH_MMIO_ADDR + ast1100_device_flash_mmio_offset, ast1100_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast1100_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast1100_disable_cpu(void) {
++	uint32_t dword;
++
++	if (ast1100_device_halt_cpu) {
++		dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP);
++		if (((dword & AST1100_SCU_BOOT_SRC_MASK) != AST1100_SCU_BOOT_SPI)
++			&& ((dword & AST1100_SCU_BOOT_SRC_MASK) != AST1100_SCU_BOOT_NONE)) {	/* NONE permitted to allow for BMC recovery after Ctrl+C or crash */
++			msg_perr("CPU halt requested but CPU firmware source is not SPI.\n");
++			pci_mmio_writel(0x0, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_PROT_KEY);
++			ast1100_device_halt_cpu = 0;
++			return 1;
++		}
++
++		/* Disable CPU */
++		ast1100_set_a2b_bridge_scu();
++		pci_mmio_writel((dword & ~AST1100_SCU_BOOT_SRC_MASK) | AST1100_SCU_BOOT_NONE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP);
++		ast1100_original_wdt_conf = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
++		pci_mmio_writel(ast1100_original_wdt_conf & 0xffff0, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
++	}
++
++	return 0;
++}
++
++static int ast1100_enable_cpu(void) {
++	uint32_t dword;
++
++	if (ast1100_device_halt_cpu && ast1100_device_resume_cpu) {
++		/* Re-enable CPU */
++		ast1100_set_a2b_bridge_scu();
++		dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP);
++		pci_mmio_writel((dword & ~AST1100_SCU_BOOT_SRC_MASK) | AST1100_SCU_BOOT_SPI, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP);
++	}
++
++	return 0;
++}
++
++static int ast1100_reset_cpu(void) {
++	if (ast1100_device_reset_cpu) {
++		/* Disable WDT from issuing full SoC reset
++		 * Without this, OpenPOWER systems will crash when the GPIO blocks are reset on WDT timeout
++		 */
++		msg_pinfo("Configuring P2A bridge for WDT access\n");
++		ast1100_set_a2b_bridge_wdt();
++		ast1100_original_wdt_conf = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
++
++		/* Initiate reset */
++		msg_pinfo("Setting WDT to reset CPU immediately\n");
++		pci_mmio_writel(ast1100_original_wdt_conf & 0xffff0, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
++		pci_mmio_writel(0xec08ce00, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR_RELOAD);
++		pci_mmio_writel(0x4755, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR_RESTART);
++		pci_mmio_writel(AST1100_WDT_SET_CLOCK, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
++		pci_mmio_writel(AST1100_WDT_RESET_SYSTEM | AST1100_WDT_ENABLE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
++	
++	}
++
++	return 0;
++}
++
++static int ast1100_shutdown(void *data) {
++	/* Reactivate CPU if previously deactivated */
++	ast1100_enable_cpu();
++
++	/* Reset CPU if requested */
++	ast1100_reset_cpu();
++
++	/* Disable backdoor APB access */
++	pci_mmio_writel(0x0, ast1100_device_bar + 0xf000);
++
++	return 0;
++}
++
++int ast1100_init(void)
++{
++	struct pci_dev *dev = NULL;
++	uint32_t dword;
++
++	char *arg;
++
++	ast1100_device_spi_bus = 0;
++	arg = extract_programmer_param("spibus");
++	if (arg)
++		ast1100_device_spi_bus = strtol(arg, NULL, 0);
++	free(arg);
++
++	ast1100_device_spi_speed = 0;
++	arg = extract_programmer_param("spispeed");
++	if (arg)
++		ast1100_device_spi_speed = strtol(arg, NULL, 0);
++	free(arg);
++
++	ast1100_device_halt_cpu = 0;
++	arg = extract_programmer_param("cpu");
++	if (arg && !strcmp(arg,"pause")) {
++		ast1100_device_halt_cpu = 1;
++		ast1100_device_resume_cpu = 1;
++		ast1100_device_reset_cpu = 0;
++	}
++	else if (arg && !strcmp(arg,"halt")) {
++		ast1100_device_halt_cpu = 1;
++		ast1100_device_resume_cpu = 0;
++		ast1100_device_reset_cpu = 0;
++	}
++	else if (arg && !strcmp(arg,"reset")) {
++		ast1100_device_halt_cpu = 1;
++		ast1100_device_resume_cpu = 1;
++		ast1100_device_reset_cpu = 1;
++	}
++	else if (arg) {
++		msg_perr("Invalid CPU option!  Valid values are: pause | halt | reset\n");
++		return 1;
++	}
++	arg = extract_programmer_param("tickle");
++	if (arg && !strcmp(arg,"true"))
++		ast1100_device_tickle_fw = 1;
++	free(arg);
++
++	if ((ast1100_device_spi_bus < 0) || (ast1100_device_spi_bus > 2)) {
++		msg_perr("SPI bus number out of range!  Valid values are 0 - 2.\n");
++		return 1;
++	}
++
++	if (rget_io_perms())
++		return 1;
++
++	dev = pcidev_init(bmc_aspeed_ast1100, PCI_BASE_ADDRESS_1);
++	if (!dev)
++		return 1;
++
++	uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_1);
++	if (!io_base_addr)
++		return 1;
++
++	msg_pinfo("Detected ASPEED MMIO base address: %p.\n", (void*)io_base_addr);
++
++	ast1100_device_bar = rphysmap("ASPEED", io_base_addr, ASPEED_MEMMAP_SIZE);
++	if (ast1100_device_bar == ERROR_PTR)
++		return 1;
++
++        if (register_shutdown(ast1100_shutdown, dev))
++                return 1;
++
++	io_base_addr += ASPEED_P2A_OFFSET;
++	msg_pinfo("ASPEED P2A base address: %p.\n", (void*)io_base_addr);
++
++	msg_pinfo("Configuring P2A bridge for SCU access\n");
++	ast1100_set_a2b_bridge_scu();
++	pci_mmio_writel(AST1100_SCU_PASSWORD, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_PROT_KEY);
++
++	/* Halt CPU if requested */
++	if (ast1100_disable_cpu())
++		return 1;
++
++	msg_pinfo("Configuring P2A bridge for SMC access\n");
++	ast1100_set_a2b_bridge_smc();
++
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00);
++	if (((dword >> ((ast1100_device_spi_bus * 2) + 4)) & 0x3) != 0x2) {
++		msg_perr("CE%01x Flash type is not SPI!\n", ast1100_device_spi_bus);
++		return 1;
++	}
++
++	msg_pinfo("Setting CE%01x SPI relative clock speed to %d\n", ast1100_device_spi_bus, ast1100_device_spi_speed);
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	dword &= ~AST1100_SPI_SPEED_MASK;
++	pci_mmio_writel(dword | ((ast1100_device_spi_speed << AST1100_SPI_SPEED_SHIFT) & AST1100_SPI_SPEED_MASK), ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++
++	msg_pinfo("Enabling CE%01x write\n", ast1100_device_spi_bus);
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00);
++	pci_mmio_writel(dword | (0x1 << (10 + ast1100_device_spi_bus)), ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00);
++
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00);
++	dword &= AST1100_SMC_SEGMENT_SIZE_MASK;
++	switch (dword & AST1100_SMC_SEGMENT_SIZE_MASK) {
++		case AST1100_SMC_SEGMENT_SIZE_32M:
++			ast1100_device_flash_mmio_offset = 0x2000000;
++			break;
++		case AST1100_SMC_SEGMENT_SIZE_16M:
++			ast1100_device_flash_mmio_offset = 0x1000000;
++			break;
++		case AST1100_SMC_SEGMENT_SIZE_8M:
++			ast1100_device_flash_mmio_offset = 0x800000;
++			break;
++		case AST1100_SMC_SEGMENT_SIZE_4M:
++			ast1100_device_flash_mmio_offset = 0x400000;
++			break;
++		default:
++			ast1100_device_flash_mmio_offset = 0x2000000;
++	}
++	msg_pinfo("Segment size: 0x%08x\n", ast1100_device_flash_mmio_offset);
++
++	ast1100_device_flash_mmio_offset = ast1100_device_flash_mmio_offset * ast1100_device_spi_bus;
++	msg_pinfo("Using CE%01x offset 0x%08x\n", ast1100_device_spi_bus, ast1100_device_flash_mmio_offset);
++
++	register_spi_master(&spi_master_ast1100);
++
++	return 0;
++}
++
++static void ast1100_spi_xfer_data(struct flashctx *flash,
++				   unsigned int writecnt, unsigned int readcnt,
++				   const unsigned char *writearr,
++				   unsigned char *readarr)
++{
++	int i;
++	uint32_t dword;
++
++	for (i = 0; i < writecnt; i++)
++		msg_pspew("[%02x]", writearr[i]);
++	msg_pspew("\n");
++
++	for (i = 0; i < writecnt; i=i+4) {
++		if ((writecnt - i) < 4)
++			break;
++		dword = writearr[i];
++		dword |= writearr[i + 1] << 8;
++		dword |= writearr[i + 2] << 16;
++		dword |= writearr[i + 3] << 24;
++		pci_mmio_writel(dword, ast1100_device_bar + ASPEED_P2A_OFFSET);
++	}
++	for (; i < writecnt; i++)
++		pci_mmio_writeb(writearr[i], ast1100_device_bar + ASPEED_P2A_OFFSET);
++	programmer_delay(1);
++	for (i = 0; i < readcnt;) {
++		dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET);
++		if (i < readcnt)
++			readarr[i] = dword & 0xff;
++		i++;
++		if (i < readcnt)
++			readarr[i] = (dword >> 8) & 0xff;
++		i++;
++		if (i < readcnt)
++			readarr[i] = (dword >> 16) & 0xff;
++		i++;
++		if (i < readcnt)
++			readarr[i] = (dword >> 24) & 0xff;
++		i++;
++	}
++
++	for (i = 0; i < readcnt; i++)
++		msg_pspew("[%02x]", readarr[i]);
++	msg_pspew("\n");
++}
++
++/* Returns 0 upon success, a negative number upon errors. */
++static int ast1100_spi_send_command(struct flashctx *flash,
++				   unsigned int writecnt, unsigned int readcnt,
++				   const unsigned char *writearr,
++				   unsigned char *readarr)
++{
++	uint32_t dword;
++
++	msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, *writearr, writecnt, readcnt);
++
++	/* Set up user command mode */
++	ast1100_set_a2b_bridge_smc();
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	pci_mmio_writel(dword | AST1100_SPI_CMD_USER_MODE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	pci_mmio_writel(dword & ~AST1100_SPI_STOP_CE_ACTIVE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++
++	/* Transfer data */
++	ast1100_set_a2b_bridge_smc_flash();
++	ast1100_spi_xfer_data(flash, writecnt, readcnt, writearr, readarr);
++
++	/* Tear down user command mode */
++	ast1100_set_a2b_bridge_smc();
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	pci_mmio_writel(dword | AST1100_SPI_STOP_CE_ACTIVE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++	pci_mmio_writel((dword & ~AST1100_SPI_CMD_MASK) | AST1100_SPI_CMD_FAST_R_MODE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus));
++
++	if (ast1100_device_tickle_fw) {
++		ast1100_enable_cpu();
++		programmer_delay(100);
++		ast1100_disable_cpu();
++	}
++
++	return 0;
++}
+diff --git ./ast2400.c ./ast2400.c
+new file mode 100644
+index 0000000..01cee76
+--- /dev/null
++++ ./ast2400.c
+@@ -0,0 +1,426 @@
++/*
++ * This file is part of the flashrom project.
++ *
++ * Copyright (C) 2016 - 2017 Raptor Engineering, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
++ */
++
++#include <stdlib.h>
++#include <string.h>
++#include "flash.h"
++#include "programmer.h"
++#include "hwaccess.h"
++
++#define PCI_VENDOR_ID_ASPEED		0x1a03
++
++#define ASPEED_MEMMAP_SIZE		(128 * 1024)
++#define ASPEED_P2A_OFFSET		0x10000
++
++#define AST2400_SCU_APB_ADDR		0x1e6e2000
++#define AST2400_SCU_APB_BRIDGE_OFFSET	(AST2400_SCU_APB_ADDR & 0xffff)
++#define AST2400_SCU_PROT_KEY		0x00
++#define AST2400_SCU_MISC_CTL		0x2c
++#define AST2400_SCU_HW_STRAP		0x70
++
++#define AST2400_SCU_PASSWORD		0x1688a8a8
++#define AST2400_SCU_BOOT_SRC_MASK	0x3
++#define AST2400_SCU_BOOT_SPI		0x2
++#define AST2400_SCU_BOOT_NONE		0x3
++
++#define AST2400_SMC_APB_ADDR		0x1e620000
++#define AST2400_SMC_FMC00		0x00
++#define AST2400_SMC_CE_CTL(N)		(0x10 + (N * 4))
++#define AST2400_SMC_CE_SEG(N)		(0x30 + (N * 4))
++
++#define AST2400_SMC_FLASH_MMIO_ADDR	0x20000000
++
++#define AST2400_SPI_APB_ADDR		0x1e630000
++#define AST2400_SPI_CFG			0x00
++#define AST2400_SPI_CTL			0x04
++
++#define AST2400_SPI_CFG_WRITE_EN	0x1
++#define AST2400_SPI_CMD_FAST_R_MODE	0x1
++#define AST2400_SPI_CMD_USER_MODE	0x3
++#define AST2400_SPI_CMD_MASK		0x3
++#define AST2400_SPI_STOP_CE_ACTIVE	(0x1 << 2)
++#define AST2400_SPI_CPOL_1		(0x1 << 4)
++#define AST2400_SPI_LSB_FIRST_CTRL	(0x1 << 5)
++#define AST2400_SPI_SPEED_MASK		(0xf << 8)
++#define AST2400_SPI_IO_MODE_MASK	(0x3 << 28)
++
++#define AST2400_SPI_FLASH_MMIO_ADDR	0x30000000
++
++#define AST2400_WDT_APB_ADDR		0x1e785000
++#define AST2400_WDT_APB_BRIDGE_OFFSET	(AST2400_WDT_APB_ADDR & 0xffff)
++
++#define AST2400_WDT1_CTL		0x0c
++
++#define AST2400_WDT_RESET_MODE_MASK	(0x3 << 5)
++#define AST2400_WDT_RESET_CPU_ONLY	(0x2 << 5)
++
++uint8_t *ast2400_device_bar = 0;
++uint8_t ast2400_device_spi_bus = 0;
++uint8_t ast2400_device_halt_cpu = 0;
++uint8_t ast2400_device_resume_cpu = 0;
++uint8_t ast2400_device_tickle_fw = 0;
++uint32_t ast2400_device_flash_mmio_offset = 0;
++uint32_t ast2400_device_host_mode = 0;
++uint32_t ast2400_original_wdt_conf = 0;
++
++const struct dev_entry bmc_aspeed_ast2400[] = {
++	{PCI_VENDOR_ID_ASPEED, 0x2000, OK, "ASPEED", "AST2400" },
++
++	{0},
++};
++
++static int ast2400_spi_send_command(struct flashctx *flash,
++				   unsigned int writecnt, unsigned int readcnt,
++				   const unsigned char *writearr,
++				   unsigned char *readarr);
++
++static const struct spi_master spi_master_ast2400 = {
++	.type		= SPI_CONTROLLER_AST2400,
++	.max_data_read	= 256,
++	.max_data_write	= 256,
++	.command	= ast2400_spi_send_command,
++	.multicommand	= default_spi_send_multicommand,
++	.read		= default_spi_read,
++	.write_256	= default_spi_write_256,
++	.write_aai	= default_spi_write_aai,
++};
++
++static int ast2400_set_a2b_bridge_scu(void)
++{
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++	pci_mmio_writel(AST2400_SCU_APB_ADDR & 0xffff0000, ast2400_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast2400_set_a2b_bridge_wdt(void)
++{
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++	pci_mmio_writel(AST2400_WDT_APB_ADDR & 0xffff0000, ast2400_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast2400_set_a2b_bridge_smc(void)
++{
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++	pci_mmio_writel(AST2400_SMC_APB_ADDR, ast2400_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast2400_set_a2b_bridge_spi(void)
++{
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++	pci_mmio_writel(AST2400_SPI_APB_ADDR, ast2400_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast2400_set_a2b_bridge_smc_flash(void)
++{
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++	pci_mmio_writel(AST2400_SMC_FLASH_MMIO_ADDR + ast2400_device_flash_mmio_offset, ast2400_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast2400_set_a2b_bridge_spi_flash(void)
++{
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++	pci_mmio_writel(AST2400_SPI_FLASH_MMIO_ADDR, ast2400_device_bar + 0xf004);
++	pci_mmio_writel(0x1, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++static int ast2400_disable_cpu(void) {
++	uint32_t dword;
++
++	if (ast2400_device_halt_cpu) {
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP);
++		if (((dword & AST2400_SCU_BOOT_SRC_MASK) != AST2400_SCU_BOOT_SPI)
++			&& ((dword & AST2400_SCU_BOOT_SRC_MASK) != AST2400_SCU_BOOT_NONE)) {	/* NONE permitted to allow for BMC recovery after Ctrl+C or crash */
++			msg_perr("CPU halt requested but CPU firmware source is not SPI.\n");
++			pci_mmio_writel(0x0, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_PROT_KEY);
++			ast2400_device_halt_cpu = 0;
++			return 1;
++		}
++
++		/* Disable WDT from issuing full SoC reset
++		 * Without this, OpenPOWER systems will crash when the GPIO blocks are reset on WDT timeout
++		 */
++		msg_pinfo("Configuring P2A bridge for WDT access\n");
++		ast2400_set_a2b_bridge_wdt();
++		ast2400_original_wdt_conf = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL);
++		pci_mmio_writel((ast2400_original_wdt_conf & ~AST2400_WDT_RESET_MODE_MASK) | AST2400_WDT_RESET_CPU_ONLY, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL);
++
++		/* Disable CPU */
++		ast2400_set_a2b_bridge_scu();
++		pci_mmio_writel((dword & ~AST2400_SCU_BOOT_SRC_MASK) | AST2400_SCU_BOOT_NONE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP);
++	}
++
++	return 0;
++}
++
++static int ast2400_enable_cpu(void) {
++	uint32_t dword;
++
++	if (ast2400_device_halt_cpu && ast2400_device_resume_cpu) {
++		/* Re-enable CPU */
++		ast2400_set_a2b_bridge_scu();
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP);
++		pci_mmio_writel((dword & ~AST2400_SCU_BOOT_SRC_MASK) | AST2400_SCU_BOOT_SPI, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP);
++
++		/* Reset WDT configuration */
++		ast2400_set_a2b_bridge_wdt();
++		pci_mmio_writel((ast2400_original_wdt_conf & ~AST2400_WDT_RESET_MODE_MASK) | AST2400_WDT_RESET_CPU_ONLY, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL);
++	}
++
++	return 0;
++}
++
++static int ast2400_shutdown(void *data) {
++	/* Reactivate CPU if previously deactivated */
++	ast2400_enable_cpu();
++
++	/* Disable backdoor APB access */
++	pci_mmio_writel(0x0, ast2400_device_bar + 0xf000);
++
++	return 0;
++}
++
++int ast2400_init(void)
++{
++	struct pci_dev *dev = NULL;
++	uint32_t dword;
++	uint8_t divisor;
++
++	char *arg;
++
++	ast2400_device_spi_bus = 0;
++	arg = extract_programmer_param("spibus");
++	if (arg) {
++		if (!strcmp(arg,"host"))
++			ast2400_device_host_mode = 1;
++		else
++			ast2400_device_spi_bus = strtol(arg, NULL, 0);
++	}
++	free(arg);
++
++	ast2400_device_halt_cpu = 0;
++	arg = extract_programmer_param("cpu");
++	if (arg && !strcmp(arg,"pause")) {
++		ast2400_device_halt_cpu = 1;
++		ast2400_device_resume_cpu = 1;
++	}
++	if (arg && !strcmp(arg,"halt")) {
++		ast2400_device_halt_cpu = 1;
++		ast2400_device_resume_cpu = 0;
++	}
++	arg = extract_programmer_param("tickle");
++	if (arg && !strcmp(arg,"true"))
++		ast2400_device_tickle_fw = 1;
++	free(arg);
++
++	if ((ast2400_device_host_mode == 0) && ((ast2400_device_spi_bus < 0) || (ast2400_device_spi_bus > 4))) {
++		msg_perr("SPI bus number out of range!  Valid values are 0 - 4.\n");
++		return 1;
++	}
++
++	if (rget_io_perms())
++		return 1;
++
++	dev = pcidev_init(bmc_aspeed_ast2400, PCI_BASE_ADDRESS_1);
++	if (!dev)
++		return 1;
++
++	uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_1);
++	if (!io_base_addr)
++		return 1;
++
++	msg_pinfo("Detected ASPEED MMIO base address: %p.\n", (void*)io_base_addr);
++
++	ast2400_device_bar = rphysmap("ASPEED", io_base_addr, ASPEED_MEMMAP_SIZE);
++	if (ast2400_device_bar == ERROR_PTR)
++		return 1;
++
++        if (register_shutdown(ast2400_shutdown, dev))
++                return 1;
++
++	io_base_addr += ASPEED_P2A_OFFSET;
++	msg_pinfo("ASPEED P2A base address: %p.\n", (void*)io_base_addr);
++
++	msg_pinfo("Configuring P2A bridge for SCU access\n");
++	ast2400_set_a2b_bridge_scu();
++	pci_mmio_writel(AST2400_SCU_PASSWORD, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_PROT_KEY);
++
++	dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_MISC_CTL);
++	pci_mmio_writel(dword & ~((0x1 << 24) | (0x2 << 22)), ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_MISC_CTL);
++
++	/* Halt CPU if requested */
++	if (ast2400_disable_cpu())
++		return 1;
++
++	msg_pinfo("Configuring P2A bridge for SMC access\n");
++	ast2400_set_a2b_bridge_smc();
++
++	if (ast2400_device_host_mode) {
++		msg_pinfo("Configuring P2A bridge for SPI access\n");
++		ast2400_set_a2b_bridge_spi();
++
++		divisor = 0;	/* Slowest speed for now */
++
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL);
++		dword &= ~AST2400_SPI_SPEED_MASK;
++		dword |= (divisor << 8);
++		dword &= ~AST2400_SPI_CPOL_1;
++		dword &= ~AST2400_SPI_LSB_FIRST_CTRL;	/* MSB first */
++		dword &= ~AST2400_SPI_IO_MODE_MASK;	/* Single bit I/O mode */
++		pci_mmio_writel(dword, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL);
++	}
++	else {
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00);
++		if (((dword >> (ast2400_device_spi_bus * 2)) & 0x3) != 0x2) {
++			msg_perr("CE%01x Flash type is not SPI!\n", ast2400_device_spi_bus);
++			return 1;
++		}
++
++		msg_pinfo("Enabling CE%01x write\n", ast2400_device_spi_bus);
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00);
++		pci_mmio_writel(dword | (0x1 << (16 + ast2400_device_spi_bus)), ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00);
++
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_SEG(ast2400_device_spi_bus));
++		ast2400_device_flash_mmio_offset = ((dword >> 16) & 0x3f) * 0x800000;
++		msg_pinfo("Using CE%01x offset 0x%08x\n", ast2400_device_spi_bus, ast2400_device_flash_mmio_offset);
++	}
++
++	register_spi_master(&spi_master_ast2400);
++
++	return 0;
++}
++
++static void ast2400_spi_xfer_data(struct flashctx *flash,
++				   unsigned int writecnt, unsigned int readcnt,
++				   const unsigned char *writearr,
++				   unsigned char *readarr)
++{
++	int i;
++	uint32_t dword;
++
++	for (i = 0; i < writecnt; i++)
++		msg_pspew("[%02x]", writearr[i]);
++	msg_pspew("\n");
++
++	for (i = 0; i < writecnt; i=i+4) {
++		if ((writecnt - i) < 4)
++			break;
++		dword = writearr[i];
++		dword |= writearr[i + 1] << 8;
++		dword |= writearr[i + 2] << 16;
++		dword |= writearr[i + 3] << 24;
++		pci_mmio_writel(dword, ast2400_device_bar + ASPEED_P2A_OFFSET);
++	}
++	for (; i < writecnt; i++)
++		pci_mmio_writeb(writearr[i], ast2400_device_bar + ASPEED_P2A_OFFSET);
++	programmer_delay(1);
++	for (i = 0; i < readcnt;) {
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET);
++		if (i < readcnt)
++			readarr[i] = dword & 0xff;
++		i++;
++		if (i < readcnt)
++			readarr[i] = (dword >> 8) & 0xff;
++		i++;
++		if (i < readcnt)
++			readarr[i] = (dword >> 16) & 0xff;
++		i++;
++		if (i < readcnt)
++			readarr[i] = (dword >> 24) & 0xff;
++		i++;
++	}
++
++	for (i = 0; i < readcnt; i++)
++		msg_pspew("[%02x]", readarr[i]);
++	msg_pspew("\n");
++}
++
++/* Returns 0 upon success, a negative number upon errors. */
++static int ast2400_spi_send_command(struct flashctx *flash,
++				   unsigned int writecnt, unsigned int readcnt,
++				   const unsigned char *writearr,
++				   unsigned char *readarr)
++{
++	uint32_t dword;
++
++	msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, *writearr, writecnt, readcnt);
++
++	if (ast2400_device_host_mode) {
++		/* Set up user command mode */
++		ast2400_set_a2b_bridge_spi();
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG);
++		pci_mmio_writel(dword | AST2400_SPI_CFG_WRITE_EN, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG);
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL);
++		pci_mmio_writel(dword | AST2400_SPI_CMD_USER_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL);
++
++	        /* Transfer data */
++		ast2400_set_a2b_bridge_spi_flash();
++		ast2400_spi_xfer_data(flash, writecnt, readcnt, writearr, readarr);
++
++		/* Tear down user command mode */
++		ast2400_set_a2b_bridge_spi();
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL);
++		pci_mmio_writel((dword & ~AST2400_SPI_CMD_MASK) | AST2400_SPI_CMD_FAST_R_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL);
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG);
++		pci_mmio_writel(dword & ~AST2400_SPI_CFG_WRITE_EN, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG);
++	}
++	else {
++		/* Set up user command mode */
++		ast2400_set_a2b_bridge_smc();
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++		pci_mmio_writel(dword | AST2400_SPI_CMD_USER_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++		pci_mmio_writel(dword & ~AST2400_SPI_STOP_CE_ACTIVE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++
++		/* Transfer data */
++		ast2400_set_a2b_bridge_smc_flash();
++		ast2400_spi_xfer_data(flash, writecnt, readcnt, writearr, readarr);
++
++		/* Tear down user command mode */
++		ast2400_set_a2b_bridge_smc();
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++		pci_mmio_writel(dword | AST2400_SPI_STOP_CE_ACTIVE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++		dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++		pci_mmio_writel((dword & ~AST2400_SPI_CMD_MASK) | AST2400_SPI_CMD_FAST_R_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus));
++	}
++
++	if (ast2400_device_tickle_fw) {
++		ast2400_enable_cpu();
++		programmer_delay(100);
++		ast2400_disable_cpu();
++	}
++
++	return 0;
++}
+diff --git ./board_enable.c ./board_enable.c
+index 2f0c1c0..758aaf4 100644
+--- ./board_enable.c
++++ ./board_enable.c
+@@ -2433,6 +2433,7 @@ const struct board_match board_matches[] = {
+ 	{0x8086, 0x27a0, 0x17aa, 0x2017,  0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL,        P2, "IBM/Lenovo",  "ThinkPad T60(s)",       0,   OK, p2_whitelist_laptop},
+ 	{0x8086, 0x2917, 0x17AA, 0x20F5,  0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200", NULL, NULL,       P2, "IBM/Lenovo",  "ThinkPad X200",         0,   OK, p2_whitelist_laptop},
+ 	{0x8086, 0x3B07, 0x17AA, 0x2166,  0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL,         P2, "IBM/Lenovo",  "ThinkPad X201",         0,   OK, p2_whitelist_laptop},
++	{0x8086, 0x1C22, 0x17AA, 0x21DB,  0x8086, 0x1C4F, 0x17AA, 0x21DB, "^ThinkPad X220", NULL, NULL,       P2, "IBM/Lenovo",  "ThinkPad X220",         0,   OK, p2_whitelist_laptop},
+ 	{0x8086, 0x1E22, 0x17AA, 0x21FA,  0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL,       P2, "IBM/Lenovo",  "ThinkPad X230",         0,   OK, p2_whitelist_laptop},
+ 	{0x8086, 0x27A0, 0x17AA, 0x2017,  0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL,        P2, "IBM/Lenovo",  "ThinkPad X60(s)",       0,   OK, p2_whitelist_laptop},
+ 	{0x8086, 0x2411, 0x8086, 0x2411,  0x8086, 0x7125, 0x0e11, 0xb165, NULL,         NULL, NULL,           P3, "Mitac",       "6513WU",                0,   OK, board_mitac_6513wu},
+diff --git ./chipdrivers.h ./chipdrivers.h
+index c85eac9..20529d5 100644
+--- ./chipdrivers.h
++++ ./chipdrivers.h
+@@ -195,4 +195,26 @@ int erase_sector_stm50(struct flashctx *flash, unsigned int block, unsigned int
+ int probe_en29lv640b(struct flashctx *flash);
+ int write_en29lv640b(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
+ 
++/* spi4ba.c */
++int spi_enter_4ba_b7(struct flashctx *flash);
++int spi_enter_4ba_b7_we(struct flashctx *flash);
++int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte);
++int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte);
++int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte);
++int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++
+ #endif /* !__CHIPDRIVERS_H__ */
+diff --git ./cli_output.c ./cli_output.c
+index feafbd2..cb82fa1 100644
+--- ./cli_output.c
++++ ./cli_output.c
+@@ -90,7 +90,8 @@ int print(enum msglevel level, const char *fmt, ...)
+ 			fflush(output_type);
+ 	}
+ #ifndef STANDALONE
+-	if ((level <= verbose_logfile) && logfile) {
++	/* skip of msgs starting from '\b' added to skip progress percents */
++	if ((level <= verbose_logfile) && logfile && (!fmt || fmt[0] != '\b')) {
+ 		va_start(ap, fmt);
+ 		ret = vfprintf(logfile, fmt, ap);
+ 		va_end(ap);
+diff --git ./flash.h ./flash.h
+index da049d1..0b72439 100644
+--- ./flash.h
++++ ./flash.h
+@@ -123,6 +123,14 @@ enum write_granularity {
+ #define FEATURE_WRSR_EITHER	(FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN)
+ #define FEATURE_OTP		(1 << 8)
+ #define FEATURE_QPI		(1 << 9)
++/* Feature bits used for 4-bytes addressing mode */
++#define FEATURE_4BA_SUPPORT		(1 << 10)
++#define FEATURE_4BA_ONLY 		(1 << 11)
++#define FEATURE_4BA_EXTENDED_ADDR_REG	(1 << 12)
++#define FEATURE_4BA_DIRECT_READ		(1 << 13)
++#define FEATURE_4BA_DIRECT_WRITE	(1 << 14)
++#define FEATURE_4BA_ALL_ERASERS_DIRECT  (1 << 15)
++#define FEATURE_4BA_ALL_DIRECT  (FEATURE_4BA_DIRECT_READ | FEATURE_4BA_DIRECT_WRITE | FEATURE_4BA_ALL_ERASERS_DIRECT)
+ 
+ enum test_state {
+ 	OK = 0,
+@@ -167,6 +175,14 @@ struct flashchip {
+ 	unsigned int page_size;
+ 	int feature_bits;
+ 
++	/* set of function pointers to use in 4-bytes addressing mode */
++	struct four_bytes_addr_funcs_set {
++		int (*enter_4ba) (struct flashctx *flash);
++		int (*read_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++		int (*program_byte) (struct flashctx *flash, unsigned int addr, const uint8_t databyte);
++		int (*program_nbyte) (struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++	} four_bytes_addr_funcs;
++
+ 	/* Indicate how well flashrom supports different operations of this flash chip. */
+ 	struct tested {
+ 		enum test_state probe;
+@@ -344,6 +360,11 @@ __attribute__((format(printf, 2, 3)));
+ #define msg_pspew(...)	print(MSG_SPEW, __VA_ARGS__)	/* programmer debug spew  */
+ #define msg_cspew(...)	print(MSG_SPEW, __VA_ARGS__)	/* chip debug spew  */
+ 
++/* Read progress will be shown for reads more than 256KB */
++#define MIN_LENGTH_TO_SHOW_READ_PROGRESS 256 * 1024
++/* Read progress will be shown for erases and writes more than 64KB */
++#define MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS 64 * 1024
++
+ /* layout.c */
+ int register_include_arg(char *name);
+ int process_include_args(void);
+diff --git ./flashchips.c ./flashchips.c
+index 40b6b8e..60baa73 100644
+--- ./flashchips.c
++++ ./flashchips.c
+@@ -8045,6 +8045,100 @@ const struct flashchip flashchips[] = {
+ 
+ 	{
+ 		.vendor		= "Macronix",
++		.name		= "MX25L25635F/MX25L25645E/MX25L25665E",
++		.bustype	= BUS_SPI,
++		.manufacture_id	= MACRONIX_ID,
++		.model_id	= MACRONIX_MX25L25635F,
++		.total_size	= 32768,
++		.page_size	= 256,
++		/* OTP: 512B total; enter 0xB1, exit 0xC1 */
++		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT,
++		.four_bytes_addr_funcs =
++		{
++			.enter_4ba = spi_enter_4ba_b7, /* enter 4-bytes addressing mode by CMD B7 */
++			.read_nbyte = spi_nbyte_read_4ba,  /* read from 4-bytes addressing mode */
++			.program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */
++			.program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */
++		},
++		.tested		= TEST_OK_PREW,
++		.probe		= probe_spi_rdid,
++		.probe_timing	= TIMING_ZERO,
++		.block_erasers	=
++		{
++			{
++				.eraseblocks = { {4 * 1024, 8192} },
++				.block_erase = spi_block_erase_20_4ba,
++			}, {
++				.eraseblocks = { {32 * 1024, 1024} },
++				.block_erase = spi_block_erase_52_4ba,
++			}, {
++				.eraseblocks = { {64 * 1024, 512} },
++				.block_erase = spi_block_erase_d8_4ba,
++			}, {
++				.eraseblocks = { {32 * 1024 * 1024, 1} },
++				.block_erase = spi_block_erase_60,
++			}, {
++				.eraseblocks = { {32 * 1024 * 1024, 1} },
++				.block_erase = spi_block_erase_c7,
++			}
++		},
++		/* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */
++		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
++		.unlock		= spi_disable_blockprotect_bp3_srwd,
++		.write		= spi_chip_write_256,
++		.read		= spi_chip_read, /* Fast read (0x0B) supported */
++		.voltage	= {2700, 3600},
++	},
++
++	{
++		.vendor		= "Macronix",
++		.name		= "MX66L51235F",
++		.bustype	= BUS_SPI,
++		.manufacture_id	= MACRONIX_ID,
++		.model_id	= MACRONIX_MX66L51235F,
++		.total_size	= 65536,
++		.page_size	= 256,
++		/* OTP: 512B total; enter 0xB1, exit 0xC1 */
++		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT,
++		.four_bytes_addr_funcs =
++		{
++			.enter_4ba = spi_enter_4ba_b7, /* enter 4-bytes addressing mode by CMD B7 */
++			.read_nbyte = spi_nbyte_read_4ba,  /* read from 4-bytes addressing mode */
++			.program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */
++			.program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */
++		},
++		.tested		= TEST_OK_PREW,
++		.probe		= probe_spi_rdid,
++		.probe_timing	= TIMING_ZERO,
++		.block_erasers	=
++		{
++			{
++				.eraseblocks = { {4 * 1024, 16384} },
++				.block_erase = spi_block_erase_20_4ba,
++			}, {
++				.eraseblocks = { {32 * 1024, 2048} },
++				.block_erase = spi_block_erase_52_4ba,
++			}, {
++				.eraseblocks = { {64 * 1024, 1024} },
++				.block_erase = spi_block_erase_d8_4ba,
++			}, {
++				.eraseblocks = { {64 * 1024 * 1024, 1} },
++				.block_erase = spi_block_erase_60,
++			}, {
++				.eraseblocks = { {64 * 1024 * 1024, 1} },
++				.block_erase = spi_block_erase_c7,
++			}
++		},
++		/* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */
++		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
++		.unlock		= spi_disable_blockprotect_bp3_srwd,
++		.write		= spi_chip_write_256,
++		.read		= spi_chip_read, /* Fast read (0x0B) supported */
++		.voltage	= {2700, 3600},
++	},
++
++	{
++		.vendor		= "Macronix",
+ 		.name		= "MX25U1635E",
+ 		.bustype	= BUS_SPI,
+ 		.manufacture_id	= MACRONIX_ID,
+@@ -11747,7 +11841,7 @@ const struct flashchip flashchips[] = {
+ 		.total_size	= 16384,
+ 		.page_size	= 256,
+ 		.feature_bits	= FEATURE_WRSR_WREN,
+-		.tested		= TEST_UNTESTED,
++		.tested		= TEST_OK_PREW,
+ 		.probe		= probe_spi_rdid,
+ 		.probe_timing	= TIMING_ZERO,
+ 		.block_erasers	= {
+@@ -14588,6 +14682,54 @@ const struct flashchip flashchips[] = {
+ 
+ 	{
+ 		.vendor		= "Winbond",
++		.name		= "W25Q256.V",
++		.bustype	= BUS_SPI,
++		.manufacture_id	= WINBOND_NEX_ID,
++		.model_id	= WINBOND_NEX_W25Q256_V,
++		.total_size	= 32768,
++		.page_size	= 256,
++		/* supports SFDP */
++		/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
++		/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
++		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_DIRECT_READ,
++		.four_bytes_addr_funcs =
++		{
++			.enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */
++			.read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */
++			.program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */
++			.program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */
++		},
++		.tested		= TEST_OK_PREW,
++		.probe		= probe_spi_rdid,
++		.probe_timing	= TIMING_ZERO,
++		.block_erasers	=
++		{
++			{
++				.eraseblocks = { {4 * 1024, 8192} },
++				.block_erase = spi_block_erase_20_4ba, /* erases 4k from 4-bytes addressing mode */
++			}, {
++				.eraseblocks = { {32 * 1024, 1024} },
++				.block_erase = spi_block_erase_52_4ba, /* erases 32k from 4-bytes addressing mode */
++			}, {
++				.eraseblocks = { {64 * 1024, 512} },
++				.block_erase = spi_block_erase_d8_4ba, /* erases 64k from 4-bytes addressing mode */
++			}, {
++				.eraseblocks = { {32 * 1024 * 1024, 1} },
++				.block_erase = spi_block_erase_60,
++			}, {
++				.eraseblocks = { {32 * 1024 * 1024, 1} },
++				.block_erase = spi_block_erase_c7,
++			}
++		},
++		.printlock	= spi_prettyprint_status_register_plain, /* TODO: improve */
++		.unlock		= spi_disable_blockprotect,
++		.write		= spi_chip_write_256,
++		.read		= spi_chip_read,
++		.voltage	= {2700, 3600},
++	},
++
++	{
++		.vendor		= "Winbond",
+ 		.name		= "W25Q20.W",
+ 		.bustype	= BUS_SPI,
+ 		.manufacture_id	= WINBOND_NEX_ID,
+diff --git ./flashchips.h ./flashchips.h
+index 9ffb30f..7171a62 100644
+--- ./flashchips.h
++++ ./flashchips.h
+@@ -482,6 +482,7 @@
+ #define MACRONIX_MX25L25635F	0x2019	/* Same as MX25L25639F, but the latter seems to not support REMS */
+ #define MACRONIX_MX25L1635D	0x2415
+ #define MACRONIX_MX25L1635E	0x2515	/* MX25L1635{E} */
++#define MACRONIX_MX66L51235F	0x201a	/* MX66L51235F */
+ #define MACRONIX_MX25U1635E	0x2535
+ #define MACRONIX_MX25U3235E	0x2536	/* Same as MX25U6435F */
+ #define MACRONIX_MX25U6435E	0x2537	/* Same as MX25U6435F */
+diff --git ./flashrom.c ./flashrom.c
+index 25e53f2..d642de8 100644
+--- ./flashrom.c
++++ ./flashrom.c
+@@ -5,6 +5,7 @@
+  * Copyright (C) 2004 Tyan Corp <yhlu@tyan.com>
+  * Copyright (C) 2005-2008 coresystems GmbH
+  * Copyright (C) 2008,2009 Carl-Daniel Hailfinger
++ * Copyright (C) 2016-2017 Raptor Engineering, LLC
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -134,6 +135,30 @@ const struct programmer_entry programmer_table[] = {
+ 	},
+ #endif
+ 
++#if CONFIG_AST1100 == 1
++	{
++		.name			= "ast1100",
++		.type			= PCI,
++		.devs.dev		= bmc_aspeed_ast1100,
++		.init			= ast1100_init,
++		.map_flash_region	= fallback_map,
++		.unmap_flash_region	= fallback_unmap,
++		.delay			= internal_delay,
++	},
++#endif
++
++#if CONFIG_AST2400 == 1
++	{
++		.name			= "ast2400",
++		.type			= PCI,
++		.devs.dev		= bmc_aspeed_ast2400,
++		.init			= ast2400_init,
++		.map_flash_region	= fallback_map,
++		.unmap_flash_region	= fallback_unmap,
++		.delay			= internal_delay,
++	},
++#endif
++
+ #if CONFIG_DRKAISER == 1
+ 	{
+ 		.name			= "drkaiser",
+@@ -1527,6 +1552,17 @@ static int walk_eraseregions(struct flashctx *flash, int erasefunction,
+ 	unsigned int start = 0;
+ 	unsigned int len;
+ 	struct block_eraser eraser = flash->chip->block_erasers[erasefunction];
++	int show_progress = 0;
++	unsigned int percent_last, percent_current;
++	unsigned long size = flash->chip->total_size * 1024;
++
++	/* progress visualizaion init */
++	if(size >= MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS) {
++		msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */
++		msg_cinfo("\b 0%%");
++		percent_last = percent_current = 0;
++		show_progress = 1; /* enable progress visualizaion */
++	}
+ 
+ 	for (i = 0; i < NUM_ERASEREGIONS; i++) {
+ 		/* count==0 for all automatically initialized array
+@@ -1544,8 +1580,20 @@ static int walk_eraseregions(struct flashctx *flash, int erasefunction,
+ 				return 1;
+ 			}
+ 			start += len;
++
++			if(show_progress) {
++				percent_current = (unsigned int) ((unsigned long long)start * 100 / size);
++				if(percent_current != percent_last) {
++					msg_cinfo("\b\b\b%2d%%", percent_current);
++					percent_last = percent_current;
++				}
++			}
+ 		}
+ 	}
++
++	if(show_progress)
++		msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */
++
+ 	msg_cdbg("\n");
+ 	return 0;
+ }
+@@ -1801,7 +1849,7 @@ void print_buildinfo(void)
+ 
+ void print_version(void)
+ {
+-	msg_ginfo("flashrom v%s", flashrom_version);
++	msg_ginfo("flashrom %s", flashrom_version);
+ 	print_sysinfo();
+ 	msg_ginfo("\n");
+ }
+@@ -1983,7 +2031,7 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it,
+ 	uint8_t *newcontents;
+ 	int ret = 0;
+ 	unsigned long size = flash->chip->total_size * 1024;
+-	int read_all_first = 1; /* FIXME: Make this configurable. */
++	int read_all_first = 0; /* FIXME: Make this configurable. */
+ 
+ 	if (chip_safety_check(flash, force, read_it, write_it, erase_it, verify_it)) {
+ 		msg_cerr("Aborting.\n");
+@@ -2001,6 +2049,44 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it,
+ 	if (flash->chip->unlock)
+ 		flash->chip->unlock(flash);
+ 
++	/* Switching to 4-Bytes Addressing mode if flash chip supports it */
++	if(flash->chip->feature_bits & FEATURE_4BA_SUPPORT) {
++		/* Do not switch if chip is already in 4-bytes addressing mode */
++		if (flash->chip->feature_bits & FEATURE_4BA_ONLY) {
++			msg_cdbg("Flash chip is already in 4-bytes addressing mode.\n");
++		}
++		/* Do not switch to 4-Bytes Addressing mode if using Extended Address Register */
++		else if(flash->chip->feature_bits & FEATURE_4BA_EXTENDED_ADDR_REG) {
++			msg_cdbg("Using 4-bytes addressing with extended address register.\n");
++		}
++		/* Go to 4-Bytes Addressing mode if selected
++		   operation requires 4-Bytes Addressing mode
++		   (no need if functions are direct-4BA) */
++		else if(((read_it || verify_it)
++			&& (!(flash->chip->feature_bits & FEATURE_4BA_DIRECT_READ)))
++		   || ((erase_it || write_it)
++			&& ((flash->chip->feature_bits & FEATURE_4BA_ALL_DIRECT) != FEATURE_4BA_ALL_DIRECT))) {
++
++			if (!flash->chip->four_bytes_addr_funcs.enter_4ba) {
++				msg_cerr("No function for Enter 4-bytes addressing mode for this flash chip.\n"
++					"Please report to flashrom@flashrom.org\n");
++				return 1;
++			}
++
++			if(flash->chip->four_bytes_addr_funcs.enter_4ba(flash)) {
++				msg_cerr("Switching to 4-bytes addressing mode failed!\n");
++				return 1;
++			}
++
++			msg_cdbg("Switched to 4-bytes addressing mode.\n");
++		}
++		/* Do not switch to 4-Bytes Addressing mode if all instructions are direct-4BA
++		   or if the flash chip is 4-Bytes Addressing Only and always in 4BA-mode */
++		else {
++			msg_cdbg2("No need to switch to 4-bytes addressing mode.\n");
++		}
++	}
++
+ 	if (read_it) {
+ 		return read_flash_to_file(flash, filename);
+ 	}
+diff --git ./layout.c ./layout.c
+index f71eeaa..2b8ce3c 100644
+--- ./layout.c
++++ ./layout.c
+@@ -259,6 +259,7 @@ int normalize_romentries(const struct flashctx *flash)
+ 
+ static int copy_old_content(struct flashctx *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents, unsigned int start, unsigned int size)
+ {
++#if 0
+ 	if (!oldcontents_valid) {
+ 		/* oldcontents is a zero-filled buffer. By reading the current data into oldcontents here, we
+ 		 * avoid a rewrite of identical regions even if an initial full chip read didn't happen. */
+@@ -269,6 +270,7 @@ static int copy_old_content(struct flashctx *flash, int oldcontents_valid, uint8
+ 			return 1;
+ 		}
+ 	}
++#endif
+ 	memcpy(newcontents + start, oldcontents + start, size);
+ 	return 0;
+ }
+diff --git ./pcidev.c ./pcidev.c
+index 2c78063..34b948b 100644
+--- ./pcidev.c
++++ ./pcidev.c
+@@ -37,11 +37,13 @@ enum pci_bartype {
+ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
+ {
+ 	uint64_t addr;
+-	uint32_t upperaddr;
+ 	uint8_t headertype;
+ 	uint16_t supported_cycles;
+ 	enum pci_bartype bartype = TYPE_UNKNOWN;
+ 
++#ifndef __PPC64__
++	uint32_t upperaddr;
++#endif
+ 
+ 	headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f;
+ 	msg_pspew("PCI header type 0x%02x\n", headertype);
+@@ -97,6 +99,12 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
+ 	switch (bartype) {
+ 	case TYPE_MEMBAR:
+ 		msg_pdbg("MEM");
++#ifdef __PPC64__
++		/* PowerPC is able to translate 32-bit BARs into 64-bit host windows.
++		 * Use the dev->base_addr[x] mechanism to handle mapping.
++		 */
++		addr = dev->base_addr[(bar - 0x10) / 0x4] & PCI_BASE_ADDRESS_MEM_MASK;
++#else
+ 		if (!(supported_cycles & PCI_COMMAND_MEMORY)) {
+ 			msg_perr("MEM BAR access requested, but device has MEM space accesses disabled.\n");
+ 			/* TODO: Abort here? */
+@@ -122,6 +130,7 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
+ 			}
+ 		}
+ 		addr &= PCI_BASE_ADDRESS_MEM_MASK;
++#endif
+ 		break;
+ 	case TYPE_IOBAR:
+ 		msg_pdbg("I/O\n");
+diff --git ./programmer.h ./programmer.h
+index bd8e98d..754f3cc 100644
+--- ./programmer.h
++++ ./programmer.h
+@@ -5,6 +5,7 @@
+  * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
+  * Copyright (C) 2005-2009 coresystems GmbH
+  * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
++ * Copyright (C) 2016-2017 Raptor Engineering, LLC
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -45,6 +46,12 @@ enum programmer {
+ #if CONFIG_GFXNVIDIA == 1
+ 	PROGRAMMER_GFXNVIDIA,
+ #endif
++#if CONFIG_AST1100 == 1
++	PROGRAMMER_AST1100,
++#endif
++#if CONFIG_AST2400 == 1
++	PROGRAMMER_AST2400,
++#endif
+ #if CONFIG_DRKAISER == 1
+ 	PROGRAMMER_DRKAISER,
+ #endif
+@@ -399,6 +406,18 @@ int gfxnvidia_init(void);
+ extern const struct dev_entry gfx_nvidia[];
+ #endif
+ 
++/* ast1100.c */
++#if CONFIG_AST1100 == 1
++int ast1100_init(void);
++extern const struct dev_entry bmc_aspeed_ast1100[];
++#endif
++
++/* ast2400.c */
++#if CONFIG_AST2400 == 1
++int ast2400_init(void);
++extern const struct dev_entry bmc_aspeed_ast2400[];
++#endif
++
+ /* drkaiser.c */
+ #if CONFIG_DRKAISER == 1
+ int drkaiser_init(void);
+@@ -600,6 +619,14 @@ enum spi_controller {
+ #if CONFIG_CH341A_SPI == 1
+ 	SPI_CONTROLLER_CH341A_SPI,
+ #endif
++
++#if CONFIG_AST1100 == 1
++	SPI_CONTROLLER_AST1100,
++#endif
++
++#if CONFIG_AST2400 == 1
++	SPI_CONTROLLER_AST2400,
++#endif
+ };
+ 
+ #define MAX_DATA_UNSPECIFIED 0
+diff --git ./serprog.c ./serprog.c
+index 98aac83..c9d98bf 100644
+--- ./serprog.c
++++ ./serprog.c
+@@ -945,7 +945,10 @@ static int serprog_spi_read(struct flashctx *flash, uint8_t *buf,
+ 	for (i = 0; i < len; i += cur_len) {
+ 		int ret;
+ 		cur_len = min(max_read, (len - i));
+-		ret = spi_nbyte_read(flash, start + i, buf + i, cur_len);
++		ret = (flash->chip->feature_bits & FEATURE_4BA_SUPPORT) == 0
++			? spi_nbyte_read(flash, start + i, buf + i, cur_len)
++			: flash->chip->four_bytes_addr_funcs.read_nbyte(flash,
++						 start + i, buf + i, cur_len);
+ 		if (ret)
+ 			return ret;
+ 	}
+diff --git ./spi.c ./spi.c
+index 894f73f..895b6a3 100644
+--- ./spi.c
++++ ./spi.c
+@@ -100,6 +100,20 @@ int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned i
  	return spi_write_chunked(flash, buf, start, len, max_data);
  }
  
@@ -22,7 +1534,19 @@ diff -u -x '*.d' -x '*.o' ../clean/flashrom-0.9.9/spi.c flashrom-0.9.9/spi.c
  int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
  		  unsigned int len)
  {
-@@ -119,7 +133,7 @@
+@@ -110,7 +124,10 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
+ 	 * means 0xffffff, the highest unsigned 24bit number.
+ 	 */
+ 	addrbase = spi_get_valid_read_addr(flash);
+-	if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) {
++	/* Show flash chip size warning if flash chip doesn't support
++	   4-Bytes Addressing mode and last address excedes 24 bits */
++	if (!(flash->chip->feature_bits & FEATURE_4BA_SUPPORT) &&
++	    addrbase + flash->chip->total_size * 1024 > (1 << 24)) {
+ 		msg_perr("Flash chip size exceeds the allowed access window. ");
+ 		msg_perr("Read will probably fail.\n");
+ 		/* Try to get the best alignment subject to constraints. */
+@@ -119,7 +136,7 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
  	/* Check if alignment is native (at least the largest power of two which
  	 * is a factor of the mapped size of the chip).
  	 */
@@ -31,3 +1555,1131 @@ diff -u -x '*.d' -x '*.o' ../clean/flashrom-0.9.9/spi.c flashrom-0.9.9/spi.c
  		msg_perr("Flash chip is not aligned natively in the allowed "
  			 "access window.\n");
  		msg_perr("Read will probably return garbage.\n");
+diff --git ./spi25.c ./spi25.c
+index af4b6db..ae5e51d 100644
+--- ./spi25.c
++++ ./spi25.c
+@@ -28,6 +28,7 @@
+ #include "chipdrivers.h"
+ #include "programmer.h"
+ #include "spi.h"
++#include "spi4ba.h"
+ 
+ static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)
+ {
+@@ -948,6 +949,16 @@ int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
+ 	int rc = 0;
+ 	unsigned int i, j, starthere, lenhere, toread;
+ 	unsigned int page_size = flash->chip->page_size;
++	int show_progress = 0;
++	unsigned int percent_last, percent_current;
++
++	/* progress visualizaion init */
++	if(len >= MIN_LENGTH_TO_SHOW_READ_PROGRESS) {
++		msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */
++		msg_cinfo("\b 0%%");
++		percent_last = percent_current = 0;
++		show_progress = 1; /* enable progress visualizaion */
++	}
+ 
+ 	/* Warning: This loop has a very unusual condition and body.
+ 	 * The loop needs to go through each page with at least one affected
+@@ -966,13 +977,28 @@ int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
+ 		lenhere = min(start + len, (i + 1) * page_size) - starthere;
+ 		for (j = 0; j < lenhere; j += chunksize) {
+ 			toread = min(chunksize, lenhere - j);
+-			rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread);
++			rc = (flash->chip->feature_bits & FEATURE_4BA_SUPPORT) == 0
++				? spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread)
++				: flash->chip->four_bytes_addr_funcs.read_nbyte(flash, starthere + j,
++					buf + starthere - start + j, toread);
+ 			if (rc)
+ 				break;
+ 		}
+ 		if (rc)
+ 			break;
++
++		if(show_progress) {
++			percent_current = (unsigned int) ((unsigned long long)(starthere +
++									lenhere - start) * 100 / len);
++			if(percent_current != percent_last) {
++				msg_cinfo("\b\b\b%2d%%", percent_current);
++				percent_last = percent_current;
+ 	}
++		}
++	}
++
++	if(show_progress && !rc)
++		msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */
+ 
+ 	return rc;
+ }
+@@ -1011,7 +1037,10 @@ int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int s
+ 		lenhere = min(start + len, (i + 1) * page_size) - starthere;
+ 		for (j = 0; j < lenhere; j += chunksize) {
+ 			towrite = min(chunksize, lenhere - j);
+-			rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
++			rc = (flash->chip->feature_bits & FEATURE_4BA_SUPPORT) == 0
++				? spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite)
++				: flash->chip->four_bytes_addr_funcs.program_nbyte(flash, starthere + j,
++					buf + starthere - start + j, towrite);
+ 			if (rc)
+ 				break;
+ 			while (spi_read_status_register(flash) & SPI_SR_WIP)
+@@ -1037,7 +1066,9 @@ int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int st
+ 	int result = 0;
+ 
+ 	for (i = start; i < start + len; i++) {
+-		result = spi_byte_program(flash, i, buf[i - start]);
++		result = (flash->chip->feature_bits & FEATURE_4BA_SUPPORT) == 0
++			? spi_byte_program(flash, i, buf[i - start])
++			: flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]);
+ 		if (result)
+ 			return 1;
+ 		while (spi_read_status_register(flash) & SPI_SR_WIP)
+diff --git ./spi4ba.c ./spi4ba.c
+new file mode 100644
+index 0000000..6e1cc9b
+--- /dev/null
++++ ./spi4ba.c
+@@ -0,0 +1,920 @@
++/*
++ * This file is part of the flashrom project.
++ *
++ * Copyright (C) 2014 Boris Baykov
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
++ */
++
++/*
++ * SPI chip driver functions for 4-bytes addressing
++ */
++
++#include <string.h>
++#include "flash.h"
++#include "chipdrivers.h"
++#include "spi.h"
++#include "programmer.h"
++#include "spi4ba.h"
++
++/* #define MSG_TRACE_4BA_FUNCS 1 */
++
++#ifdef MSG_TRACE_4BA_FUNCS
++#define msg_trace(...) print(MSG_DEBUG, __VA_ARGS__)
++#else
++#define msg_trace(...)
++#endif
++
++/* Enter 4-bytes addressing mode (without sending WREN before) */
++int spi_enter_4ba_b7(struct flashctx *flash)
++{
++	const unsigned char cmd[JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_ENTER_4_BYTE_ADDR_MODE };
++
++	msg_trace("-> %s\n", __func__);
++
++	/* Switch to 4-bytes addressing mode  */
++	return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
++}
++
++/* Enter 4-bytes addressing mode with sending WREN before */
++int spi_enter_4ba_b7_we(struct flashctx *flash)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_ENTER_4_BYTE_ADDR_MODE },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s\n", __func__);
++
++	/* Switch to 4-bytes addressing mode  */
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution\n", __func__);
++	}
++	return result;
++}
++
++/* Program one flash byte from 4-bytes addressing mode */
++int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr,
++				 uint8_t databyte)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BYTE_PROGRAM_OUTSIZE + 1,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BYTE_PROGRAM,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff),
++					databyte
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X)\n", __func__, addr);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++	}
++	return result;
++}
++
++/* Program flash bytes from 4-bytes addressing mode */
++int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr,
++			  const uint8_t *bytes, unsigned int len)
++{
++	int result;
++	unsigned char cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + 256] = {
++		JEDEC_BYTE_PROGRAM,
++		(addr >> 24) & 0xff,
++		(addr >> 16) & 0xff,
++		(addr >> 8) & 0xff,
++		(addr >> 0) & 0xff
++	};
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= (JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + len,
++		.writearr	= cmd,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1);
++
++	if (!len) {
++		msg_cerr("%s called for zero-length write\n", __func__);
++		return 1;
++	}
++	if (len > 256) {
++		msg_cerr("%s called for too long a write\n", __func__);
++		return 1;
++	}
++
++	memcpy(&cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1], bytes, len);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++	}
++	return result;
++}
++
++/* Read flash bytes from 4-bytes addressing mode */
++int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr,
++		   uint8_t *bytes, unsigned int len)
++{
++	const unsigned char cmd[JEDEC_READ_OUTSIZE + 1] = {
++		JEDEC_READ,
++		(addr >> 24) & 0xff,
++		(addr >> 16) & 0xff,
++		(addr >> 8) & 0xff,
++		(addr >> 0) & 0xff
++	};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1);
++
++	/* Send Read */
++	return spi_send_command(flash, sizeof(cmd), len, cmd, bytes);
++}
++
++/* Erases 4 KB of flash from 4-bytes addressing mode */
++int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_SE_OUTSIZE + 1,
++		.writearr	= (const unsigned char[]){
++					JEDEC_SE,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 15-800 ms, so wait in 10 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(10 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Erases 32 KB of flash from 4-bytes addressing mode */
++int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BE_52_OUTSIZE + 1,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BE_52,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(100 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Erases 64 KB of flash from 4-bytes addressing mode */
++int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BE_D8_OUTSIZE + 1,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BE_D8,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(100 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Write Extended Address Register value */
++int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_WRITE_EXT_ADDR_REG,
++					regdata
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (%02X)\n", __func__, regdata);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution\n", __func__);
++		return result;
++	}
++	return 0;
++}
++
++/* Assign required value of Extended Address Register. This function
++   keeps last value of the register and writes the register if the
++   value has to be changed only. */
++int set_extended_address_register(struct flashctx *flash, uint8_t data)
++{
++	static uint8_t ext_addr_reg_state; /* memory for last register state */
++	static int ext_addr_reg_state_valid = 0;
++	int result;
++
++	if (ext_addr_reg_state_valid == 0 || data != ext_addr_reg_state) {
++		result = spi_write_extended_address_register(flash, data);
++		if (result) {
++			ext_addr_reg_state_valid = 0;
++			return result;
++		}
++		ext_addr_reg_state = data;
++		ext_addr_reg_state_valid = 1;
++	}
++	return 0;
++}
++
++/* Program one flash byte using Extended Address Register
++   from 3-bytes addressing mode */
++int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr,
++				 uint8_t databyte)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BYTE_PROGRAM_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BYTE_PROGRAM,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff),
++					databyte
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X)\n", __func__, addr);
++
++	result = set_extended_address_register(flash, (addr >> 24) & 0xff);
++	if (result)
++		return result;
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++	}
++	return result;
++}
++
++/* Program flash bytes using Extended Address Register
++   from 3-bytes addressing mode */
++int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr,
++				  const uint8_t *bytes, unsigned int len)
++{
++	int result;
++	unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
++		JEDEC_BYTE_PROGRAM,
++		(addr >> 16) & 0xff,
++		(addr >> 8) & 0xff,
++		(addr >> 0) & 0xff
++	};
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
++		.writearr	= cmd,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1);
++
++	if (!len) {
++		msg_cerr("%s called for zero-length write\n", __func__);
++		return 1;
++	}
++	if (len > 256) {
++		msg_cerr("%s called for too long a write\n", __func__);
++		return 1;
++	}
++
++	memcpy(&cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1], bytes, len);
++
++	result = set_extended_address_register(flash, (addr >> 24) & 0xff);
++	if (result)
++		return result;
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++	}
++	return result;
++}
++
++/* Read flash bytes using Extended Address Register
++   from 3-bytes addressing mode */
++int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr,
++		   uint8_t *bytes, unsigned int len)
++{
++	int result;
++	const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
++		JEDEC_READ,
++		(addr >> 16) & 0xff,
++		(addr >> 8) & 0xff,
++		(addr >> 0) & 0xff
++	};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1);
++
++	result = set_extended_address_register(flash, (addr >> 24) & 0xff);
++	if (result)
++		return result;
++
++	/* Send Read */
++	return spi_send_command(flash, sizeof(cmd), len, cmd, bytes);
++}
++
++/* Erases 4 KB of flash using Extended Address Register
++   from 3-bytes addressing mode */
++int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_SE_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_SE,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = set_extended_address_register(flash, (addr >> 24) & 0xff);
++	if (result)
++		return result;
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 15-800 ms, so wait in 10 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(10 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Erases 32 KB of flash using Extended Address Register
++   from 3-bytes addressing mode */
++int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BE_52_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BE_52,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = set_extended_address_register(flash, (addr >> 24) & 0xff);
++	if (result)
++		return result;
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(100 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Erases 64 KB of flash using Extended Address Register
++   from 3-bytes addressing mode */
++int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BE_D8_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BE_D8,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = set_extended_address_register(flash, (addr >> 24) & 0xff);
++	if (result)
++		return result;
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(100 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Program one flash byte with 4-bytes address from ANY mode (3-bytes or 4-bytes)
++   JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips.
++   The presence of this instruction for an exact chip should be checked
++   by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
++int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr,
++				 uint8_t databyte)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BYTE_PROGRAM_4BA_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BYTE_PROGRAM_4BA,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff),
++					databyte
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X)\n", __func__, addr);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++	}
++	return result;
++}
++
++/* Program flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes)
++   JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips.
++   The presence of this instruction for an exact chip should be checked
++   by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
++int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr,
++				  const uint8_t *bytes, unsigned int len)
++{
++	int result;
++	unsigned char cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + 256] = {
++		JEDEC_BYTE_PROGRAM_4BA,
++		(addr >> 24) & 0xff,
++		(addr >> 16) & 0xff,
++		(addr >> 8) & 0xff,
++		(addr >> 0) & 0xff
++	};
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + len,
++		.writearr	= cmd,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1);
++
++	if (!len) {
++		msg_cerr("%s called for zero-length write\n", __func__);
++		return 1;
++	}
++	if (len > 256) {
++		msg_cerr("%s called for too long a write\n", __func__);
++		return 1;
++	}
++
++	memcpy(&cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1], bytes, len);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++	}
++	return result;
++}
++
++/* Read flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes)
++   JEDEC_READ_4BA (13h) instruction is new for 4-bytes addressing flash chips.
++   The presence of this instruction for an exact chip should be checked
++   by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
++int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr,
++		   uint8_t *bytes, unsigned int len)
++{
++	const unsigned char cmd[JEDEC_READ_4BA_OUTSIZE] = {
++		JEDEC_READ_4BA,
++		(addr >> 24) & 0xff,
++		(addr >> 16) & 0xff,
++		(addr >> 8) & 0xff,
++		(addr >> 0) & 0xff
++	};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1);
++
++	/* Send Read */
++	return spi_send_command(flash, sizeof(cmd), len, cmd, bytes);
++}
++
++/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes)
++   JEDEC_SE_4BA (21h) instruction is new for 4-bytes addressing flash chips.
++   The presence of this instruction for an exact chip should be checked
++   by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
++int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr,
++				   unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_SE_4BA_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_SE_4BA,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 15-800 ms, so wait in 10 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(10 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes)
++   JEDEC_BE_5C_4BA (5Ch) instruction is new for 4-bytes addressing flash chips.
++   The presence of this instruction for an exact chip should be checked
++   by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
++int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr,
++		       unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BE_5C_4BA_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BE_5C_4BA,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(100 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
++
++/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes)
++   JEDEC_BE_DC_4BA (DCh) instruction is new for 4-bytes addressing flash chips.
++   The presence of this instruction for an exact chip should be checked
++   by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */
++int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr,
++				   unsigned int blocklen)
++{
++	int result;
++	struct spi_command cmds[] = {
++	{
++		.writecnt	= JEDEC_WREN_OUTSIZE,
++		.writearr	= (const unsigned char[]){ JEDEC_WREN },
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= JEDEC_BE_DC_4BA_OUTSIZE,
++		.writearr	= (const unsigned char[]){
++					JEDEC_BE_DC_4BA,
++					(addr >> 24) & 0xff,
++					(addr >> 16) & 0xff,
++					(addr >> 8) & 0xff,
++					(addr & 0xff)
++				},
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}, {
++		.writecnt	= 0,
++		.writearr	= NULL,
++		.readcnt	= 0,
++		.readarr	= NULL,
++	}};
++
++	msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1);
++
++	result = spi_send_multicommand(flash, cmds);
++	if (result) {
++		msg_cerr("%s failed during command execution at address 0x%x\n",
++			__func__, addr);
++		return result;
++	}
++	/* Wait until the Write-In-Progress bit is cleared.
++	 * This usually takes 100-4000 ms, so wait in 100 ms steps.
++	 */
++	while (spi_read_status_register(flash) & SPI_SR_WIP)
++		programmer_delay(100 * 1000);
++	/* FIXME: Check the status register for errors. */
++	return 0;
++}
+diff --git ./spi4ba.h ./spi4ba.h
+new file mode 100644
+index 0000000..8e500d1
+--- /dev/null
++++ ./spi4ba.h
+@@ -0,0 +1,114 @@
++/*
++ * This file is part of the flashrom project.
++ *
++ * Copyright (C) 2014 Boris Baykov
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
++*/
++
++/*
++ * JEDEC flash chips instructions for 4-bytes addressing
++ * SPI chip driver functions for 4-bytes addressing
++ */
++
++#ifndef __SPI_4BA_H__
++#define __SPI_4BA_H__ 1
++
++/* Enter 4-byte Address Mode */
++#define JEDEC_ENTER_4_BYTE_ADDR_MODE		0xB7
++#define JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE	0x01
++#define JEDEC_ENTER_4_BYTE_ADDR_MODE_INSIZE	0x00
++
++/* Exit 4-byte Address Mode */
++#define JEDEC_EXIT_4_BYTE_ADDR_MODE		0xE9
++#define JEDEC_EXIT_4_BYTE_ADDR_MODE_OUTSIZE	0x01
++#define JEDEC_EXIT_4_BYTE_ADDR_MODE_INSIZE	0x00
++
++/* Write Extended Address Register */
++#define JEDEC_WRITE_EXT_ADDR_REG		0xC5
++#define JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE	0x02
++#define JEDEC_WRITE_EXT_ADDR_REG_INSIZE		0x00
++
++/* Read Extended Address Register */
++#define JEDEC_READ_EXT_ADDR_REG			0xC8
++#define JEDEC_READ_EXT_ADDR_REG_OUTSIZE		0x01
++#define JEDEC_READ_EXT_ADDR_REG_INSIZE		0x01
++
++/* Read the memory with 4-byte address
++   From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
++#define JEDEC_READ_4BA		0x13
++#define JEDEC_READ_4BA_OUTSIZE	0x05
++/*      JEDEC_READ_4BA_INSIZE : any length */
++
++/* Write memory byte with 4-byte address
++   From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
++#define JEDEC_BYTE_PROGRAM_4BA		0x12
++#define JEDEC_BYTE_PROGRAM_4BA_OUTSIZE	0x06
++#define JEDEC_BYTE_PROGRAM_4BA_INSIZE	0x00
++
++/* Sector Erase 0x21 (with 4-byte address), usually 4k size.
++   From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
++#define JEDEC_SE_4BA		0x21
++#define JEDEC_SE_4BA_OUTSIZE	0x05
++#define JEDEC_SE_4BA_INSIZE	0x00
++
++/* Block Erase 0x5C (with 4-byte address), usually 32k size.
++   From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
++#define JEDEC_BE_5C_4BA		0x5C
++#define JEDEC_BE_5C_4BA_OUTSIZE	0x05
++#define JEDEC_BE_5C_4BA_INSIZE	0x00
++
++/* Block Erase 0xDC (with 4-byte address), usually 64k size.
++   From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
++#define JEDEC_BE_DC_4BA		0xdc
++#define JEDEC_BE_DC_4BA_OUTSIZE	0x05
++#define JEDEC_BE_DC_4BA_INSIZE	0x00
++
++/* enter 4-bytes addressing mode */
++int spi_enter_4ba_b7(struct flashctx *flash);
++int spi_enter_4ba_b7_we(struct flashctx *flash);
++
++/* read/write flash bytes in 4-bytes addressing mode */
++int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte);
++int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++
++/* erase flash bytes in 4-bytes addressing mode */
++int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++
++/* read/write flash bytes from 3-bytes addressing mode using extended address register */
++int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte);
++int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++
++/* erase flash bytes from 3-bytes addressing mode using extended address register */
++int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++
++/* read/write flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */
++int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte);
++int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len);
++int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len);
++
++/* erase flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */
++int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
++
++
++#endif /* __SPI_4BA_H__ */