2023-12-15 16:27:05 +00:00
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#
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# Automatically generated file; DO NOT EDIT.
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# coreboot configuration
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#
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#
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# General setup
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#
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CONFIG_COREBOOT_BUILD=y
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CONFIG_LOCALVERSION=""
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CONFIG_CBFS_PREFIX="fallback"
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CONFIG_COMPILER_GCC=y
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# CONFIG_COMPILER_LLVM_CLANG is not set
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CONFIG_ARCH_SUPPORTS_CLANG=y
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# CONFIG_ANY_TOOLCHAIN is not set
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# CONFIG_CCACHE is not set
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# CONFIG_IWYU is not set
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# CONFIG_FMD_GENPARSER is not set
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# CONFIG_UTIL_GENPARSER is not set
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CONFIG_OPTION_BACKEND_NONE=y
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CONFIG_COMPRESS_RAMSTAGE_LZMA=y
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# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
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2023-10-11 13:06:06 +00:00
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CONFIG_SEPARATE_ROMSTAGE=y
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2023-12-15 16:27:05 +00:00
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CONFIG_INCLUDE_CONFIG_FILE=y
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CONFIG_COLLECT_TIMESTAMPS=y
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# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
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CONFIG_USE_BLOBS=y
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# CONFIG_USE_AMD_BLOBS is not set
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# CONFIG_USE_QC_BLOBS is not set
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# CONFIG_COVERAGE is not set
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# CONFIG_UBSAN is not set
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CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
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# CONFIG_ASAN is not set
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# CONFIG_NO_STAGE_CACHE is not set
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CONFIG_TSEG_STAGE_CACHE=y
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# CONFIG_UPDATE_IMAGE is not set
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2023-12-15 16:33:27 +00:00
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CONFIG_BOOTSPLASH_IMAGE=y
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CONFIG_BOOTSPLASH_FILE="@BRAND_DIR@/bootsplash.jpg"
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CONFIG_BOOTSPLASH_CONVERT=y
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CONFIG_BOOTSPLASH_CONVERT_QUALITY=70
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# CONFIG_BOOTSPLASH_CONVERT_RESIZE is not set
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# CONFIG_BOOTSPLASH_CONVERT_COLORSWAP is not set
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2023-12-15 16:27:05 +00:00
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# CONFIG_FW_CONFIG is not set
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#
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# Software Bill Of Materials (SBOM)
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#
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# CONFIG_SBOM is not set
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# end of Software Bill Of Materials (SBOM)
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# end of General setup
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#
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# Mainboard
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#
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#
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# Important: Run 'make distclean' before switching boards
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#
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# CONFIG_VENDOR_51NB is not set
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# CONFIG_VENDOR_ACER is not set
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# CONFIG_VENDOR_ADLINK is not set
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# CONFIG_VENDOR_AMD is not set
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# CONFIG_VENDOR_AOPEN is not set
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# CONFIG_VENDOR_APPLE is not set
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# CONFIG_VENDOR_ASROCK is not set
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# CONFIG_VENDOR_ASUS is not set
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# CONFIG_VENDOR_BIOSTAR is not set
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# CONFIG_VENDOR_BOSTENTECH is not set
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# CONFIG_VENDOR_BYTEDANCE is not set
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# CONFIG_VENDOR_CAVIUM is not set
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# CONFIG_VENDOR_CLEVO is not set
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# CONFIG_VENDOR_COMPULAB is not set
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# CONFIG_VENDOR_DELL is not set
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# CONFIG_VENDOR_EMULATION is not set
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# CONFIG_VENDOR_EXAMPLE is not set
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# CONFIG_VENDOR_FACEBOOK is not set
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# CONFIG_VENDOR_FOXCONN is not set
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# CONFIG_VENDOR_GETAC is not set
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# CONFIG_VENDOR_GIGABYTE is not set
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# CONFIG_VENDOR_GOOGLE is not set
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# CONFIG_VENDOR_HP is not set
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# CONFIG_VENDOR_IBASE is not set
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# CONFIG_VENDOR_IBM is not set
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# CONFIG_VENDOR_INTEL is not set
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# CONFIG_VENDOR_INVENTEC is not set
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# CONFIG_VENDOR_KONTRON is not set
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# CONFIG_VENDOR_LENOVO is not set
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# CONFIG_VENDOR_LIBRETREND is not set
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# CONFIG_VENDOR_MSI is not set
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# CONFIG_VENDOR_OCP is not set
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# CONFIG_VENDOR_OPENCELLULAR is not set
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# CONFIG_VENDOR_PACKARDBELL is not set
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# CONFIG_VENDOR_PCENGINES is not set
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# CONFIG_VENDOR_PINE64 is not set
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# CONFIG_VENDOR_PORTWELL is not set
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# CONFIG_VENDOR_PRODRIVE is not set
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# CONFIG_VENDOR_PROTECTLI is not set
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2020-12-04 18:46:03 +00:00
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CONFIG_VENDOR_PURISM=y
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2023-12-15 16:27:05 +00:00
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# CONFIG_VENDOR_RAZER is not set
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# CONFIG_VENDOR_RODA is not set
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# CONFIG_VENDOR_SAMSUNG is not set
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# CONFIG_VENDOR_SAPPHIRE is not set
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# CONFIG_VENDOR_SIEMENS is not set
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# CONFIG_VENDOR_SIFIVE is not set
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# CONFIG_VENDOR_STARLABS is not set
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# CONFIG_VENDOR_SUPERMICRO is not set
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# CONFIG_VENDOR_SYSTEM76 is not set
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# CONFIG_VENDOR_TI is not set
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# CONFIG_VENDOR_UP is not set
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CONFIG_MAINBOARD_FAMILY="Librem 14"
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CONFIG_MAINBOARD_PART_NUMBER="Librem 14"
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CONFIG_MAINBOARD_VERSION="1.0"
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CONFIG_MAINBOARD_DIR="purism/librem_cnl"
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CONFIG_VGA_BIOS_ID="8086,9b41"
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CONFIG_DIMM_MAX=2
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CONFIG_DIMM_SPD_SIZE=512
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CONFIG_FMDFILE=""
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CONFIG_NO_POST=y
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CONFIG_MAINBOARD_VENDOR="Purism"
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CONFIG_CBFS_SIZE=0xC00000
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2023-08-29 18:01:27 +00:00
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CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
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CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
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2023-12-15 16:27:05 +00:00
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CONFIG_MAX_CPUS=12
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# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
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CONFIG_DEVICETREE="devicetree.cb"
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# CONFIG_VBOOT is not set
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CONFIG_VARIANT_DIR="librem_14"
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CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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# CONFIG_VGA_BIOS is not set
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CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Purism"
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CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
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# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
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CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xe00
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CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
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CONFIG_TPM_PIRQ=0x0
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CONFIG_PXE_ROM_ID="10ec,8168"
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CONFIG_USE_PM_ACPI_TIMER=y
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CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
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CONFIG_ECAM_MMCONF_BUS_NUMBER=256
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CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
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CONFIG_DCACHE_RAM_BASE=0xfef00000
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CONFIG_DCACHE_RAM_SIZE=0x40000
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CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
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CONFIG_DCACHE_BSP_STACK_SIZE=0x20400
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CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
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CONFIG_HAVE_INTEL_FIRMWARE=y
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CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
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CONFIG_DRIVERS_INTEL_WIFI=y
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2020-12-04 18:46:03 +00:00
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CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/librem_14/flashdescriptor.bin"
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CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/librem_14/me.bin"
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2023-12-15 16:27:05 +00:00
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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CONFIG_CARDBUS_PLUGIN_SUPPORT=y
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CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
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modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
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# CONFIG_USE_LEGACY_8254_TIMER is not set
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2023-12-15 16:27:05 +00:00
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# CONFIG_DEBUG_SMI is not set
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CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Librem 14"
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2020-12-04 18:46:03 +00:00
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CONFIG_HAVE_IFD_BIN=y
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2023-12-15 16:27:05 +00:00
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CONFIG_PS2K_EISAID="PNP0303"
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CONFIG_PS2M_EISAID="PNP0F13"
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CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
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# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
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CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
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CONFIG_D3COLD_SUPPORT=y
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CONFIG_PCIEXP_ASPM=y
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CONFIG_PCIEXP_L1_SUB_STATE=y
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CONFIG_PCIEXP_CLK_PM=y
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CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
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# CONFIG_BOARD_PURISM_LIBREM13_V1 is not set
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# CONFIG_BOARD_PURISM_LIBREM15_V2 is not set
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# CONFIG_BOARD_PURISM_LIBREM_MINI is not set
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# CONFIG_BOARD_PURISM_LIBREM_MINI_V2 is not set
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2020-12-04 18:46:03 +00:00
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CONFIG_BOARD_PURISM_LIBREM_14=y
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2023-12-15 16:27:05 +00:00
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# CONFIG_BOARD_PURISM_LIBREM_11 is not set
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# CONFIG_BOARD_PURISM_LIBREM_L1UM_V2 is not set
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# CONFIG_BOARD_PURISM_LIBREM13_V2 is not set
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# CONFIG_BOARD_PURISM_LIBREM15_V3 is not set
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# CONFIG_BOARD_PURISM_LIBREM13_V4 is not set
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# CONFIG_BOARD_PURISM_LIBREM15_V4 is not set
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# CONFIG_DRIVERS_UART_8250IO is not set
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CONFIG_BOARD_PURISM_BASEBOARD_LIBREM_CNL=y
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CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
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CONFIG_FSP_TEMP_RAM_SIZE=0x10000
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CONFIG_EC_GPE_SCI=0x50
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CONFIG_TPM_MEASURED_BOOT=y
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CONFIG_LINUX_COMMAND_LINE="quiet loglevel=2"
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CONFIG_BOARD_ROMSIZE_KB_16384=y
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# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
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CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
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# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
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2023-12-15 16:27:05 +00:00
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# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
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CONFIG_COREBOOT_ROMSIZE_KB=16384
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CONFIG_ROM_SIZE=0x01000000
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CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
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CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
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# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
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CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
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# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
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CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
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# end of Mainboard
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CONFIG_SYSTEM_TYPE_LAPTOP=y
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#
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# Chipset
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#
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#
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# SoC
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#
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2023-10-11 13:06:06 +00:00
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CONFIG_CHIPSET_DEVICETREE="soc/intel/cannonlake/chipset.cb"
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2023-12-15 16:27:05 +00:00
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CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd"
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CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd"
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CONFIG_CBFS_MCACHE_SIZE=0x4000
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CONFIG_ROMSTAGE_ADDR=0x2000000
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CONFIG_VERSTAGE_ADDR=0x2000000
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CONFIG_SMM_TSEG_SIZE=0x800000
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CONFIG_SMM_RESERVED_SIZE=0x200000
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CONFIG_SMM_MODULE_STACK_SIZE=0x800
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CONFIG_ACPI_BERT_SIZE=0x0
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CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=216
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2023-10-11 13:06:06 +00:00
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CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
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CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
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2023-12-15 16:27:05 +00:00
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CONFIG_ACPI_CPU_STRING="CP%02X"
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CONFIG_STACK_SIZE=0x2000
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CONFIG_IFD_CHIPSET="cnl"
|
|
|
|
CONFIG_IED_REGION_SIZE=0x400000
|
|
|
|
CONFIG_MAX_ROOT_PORTS=16
|
|
|
|
CONFIG_MAX_PCIE_CLOCK_SRC=6
|
|
|
|
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
|
|
|
CONFIG_CPU_BCLK_MHZ=100
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
|
|
|
CONFIG_CPU_XTAL_HZ=24000000
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=3
|
|
|
|
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
|
|
|
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
|
|
|
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/"
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_FSP_FD_PATH="3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd"
|
|
|
|
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8258
|
|
|
|
CONFIG_INTEL_GMA_BCLV_WIDTH=32
|
|
|
|
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8254
|
|
|
|
CONFIG_INTEL_GMA_BCLM_WIDTH=32
|
|
|
|
CONFIG_MAX_HECI_DEVICES=6
|
|
|
|
CONFIG_BOOTBLOCK_IN_CBFS=y
|
|
|
|
CONFIG_HAVE_PAM0_REGISTER=y
|
|
|
|
CONFIG_PCIEXP_COMMON_CLOCK=y
|
|
|
|
CONFIG_SOC_INTEL_CANNONLAKE_BASE=y
|
|
|
|
CONFIG_SOC_INTEL_COMETLAKE=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_SOC_INTEL_COMETLAKE_1_2=y
|
|
|
|
CONFIG_FSP_FD_PATH_2="3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd"
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT=0
|
|
|
|
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
|
|
|
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
|
|
|
|
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
|
|
|
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
|
|
|
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
|
|
|
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
|
|
|
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
|
|
|
CONFIG_CBFS_CACHE_ALIGN=8
|
|
|
|
CONFIG_SOC_INTEL_COMMON=y
|
|
|
|
|
|
|
|
#
|
|
|
|
# Intel SoC Common Code for IP blocks
|
|
|
|
#
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CNVI=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
|
|
|
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
|
|
|
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
|
|
|
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
|
|
|
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
|
|
|
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
|
|
|
CONFIG_HAVE_HYPERTHREADING=y
|
|
|
|
CONFIG_FSP_HYPERTHREADING=y
|
|
|
|
# CONFIG_INTEL_KEYLOCKER is not set
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC=y
|
|
|
|
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME="ME_RW_A"
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME="ME_RW_B"
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME="me_rw.hash"
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
|
|
|
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
|
|
|
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
|
|
|
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
|
|
|
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
|
|
|
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
|
|
|
CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ME_SPEC_12=y
|
|
|
|
CONFIG_ME_SPEC=12
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_DTT=y
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
|
|
|
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
|
|
|
CONFIG_SOC_INTEL_CONFIGURE_DDI_A_4_LANES=y
|
|
|
|
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_IRQ=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
|
|
|
CONFIG_SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION=y
|
|
|
|
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
|
|
|
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
|
|
|
|
|
|
|
#
|
|
|
|
# Intel SoC Common PCH Code
|
|
|
|
#
|
|
|
|
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
|
|
|
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
|
|
|
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
|
|
|
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
|
|
|
|
|
|
|
#
|
|
|
|
# Intel SoC Common coreboot stages and non-IP blocks
|
|
|
|
#
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_BASECODE_RAMTOP=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_RESET=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
|
|
|
CONFIG_PAVP=y
|
|
|
|
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
|
|
|
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
|
|
|
|
|
|
|
#
|
|
|
|
# CPU
|
|
|
|
#
|
|
|
|
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
|
|
|
CONFIG_CPU_INTEL_COMMON=y
|
|
|
|
CONFIG_ENABLE_VMX=y
|
|
|
|
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
|
|
|
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
|
|
|
CONFIG_CPU_INTEL_COMMON_SMM=y
|
|
|
|
CONFIG_PARALLEL_MP=y
|
|
|
|
CONFIG_PARALLEL_MP_AP_WORK=y
|
|
|
|
CONFIG_XAPIC_ONLY=y
|
|
|
|
# CONFIG_X2APIC_ONLY is not set
|
|
|
|
# CONFIG_X2APIC_RUNTIME is not set
|
|
|
|
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
|
|
|
CONFIG_UDELAY_TSC=y
|
|
|
|
CONFIG_TSC_MONOTONIC_TIMER=y
|
|
|
|
CONFIG_X86_CLFLUSH_CAR=y
|
|
|
|
CONFIG_HAVE_SMI_HANDLER=y
|
|
|
|
CONFIG_SMM_TSEG=y
|
|
|
|
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
|
|
|
CONFIG_AP_STACK_SIZE=0x800
|
|
|
|
CONFIG_SMP=y
|
|
|
|
CONFIG_SSE=y
|
|
|
|
CONFIG_SSE2=y
|
|
|
|
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
|
|
|
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
|
|
|
# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
|
2020-12-04 18:46:03 +00:00
|
|
|
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
|
2023-12-15 16:27:05 +00:00
|
|
|
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
|
|
|
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
2020-12-04 18:46:03 +00:00
|
|
|
CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin"
|
2023-12-15 16:27:05 +00:00
|
|
|
|
|
|
|
#
|
|
|
|
# Northbridge
|
|
|
|
#
|
|
|
|
|
|
|
|
#
|
|
|
|
# Southbridge
|
|
|
|
#
|
|
|
|
# CONFIG_PCIEXP_HOTPLUG is not set
|
|
|
|
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
|
|
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
|
|
|
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
|
|
|
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
|
|
|
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
|
|
|
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
|
|
|
CONFIG_RCBA_LENGTH=0x4000
|
|
|
|
|
|
|
|
#
|
|
|
|
# Super I/O
|
|
|
|
#
|
|
|
|
|
|
|
|
#
|
|
|
|
# Embedded Controllers
|
|
|
|
#
|
|
|
|
CONFIG_EC_LIBREM_EC=y
|
|
|
|
|
|
|
|
#
|
|
|
|
# Intel Firmware
|
|
|
|
#
|
2020-12-04 18:46:03 +00:00
|
|
|
CONFIG_HAVE_ME_BIN=y
|
2023-12-15 16:27:05 +00:00
|
|
|
# CONFIG_STITCH_ME_BIN is not set
|
|
|
|
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
|
|
|
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
|
|
|
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
|
|
|
CONFIG_UNLOCK_FLASH_REGIONS=y
|
|
|
|
CONFIG_UDK_BASE=y
|
|
|
|
CONFIG_UDK_2017_BINDING=y
|
|
|
|
CONFIG_UDK_2013_VERSION=2013
|
|
|
|
CONFIG_UDK_2017_VERSION=2017
|
|
|
|
CONFIG_UDK_202005_VERSION=202005
|
|
|
|
CONFIG_UDK_202302_VERSION=202302
|
|
|
|
CONFIG_UDK_VERSION=2017
|
|
|
|
CONFIG_ARCH_X86=y
|
|
|
|
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
|
|
|
CONFIG_ARCH_VERSTAGE_X86_32=y
|
|
|
|
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
|
|
|
CONFIG_ARCH_POSTCAR_X86_32=y
|
|
|
|
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
|
|
|
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
|
|
|
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_PC80_SYSTEM=y
|
|
|
|
CONFIG_POSTCAR_STAGE=y
|
|
|
|
CONFIG_BOOTBLOCK_SIMPLE=y
|
|
|
|
# CONFIG_BOOTBLOCK_NORMAL is not set
|
|
|
|
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
|
|
|
CONFIG_IDT_IN_EVERY_STAGE=y
|
|
|
|
CONFIG_HAVE_CF9_RESET=y
|
|
|
|
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
|
|
|
CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES=y
|
|
|
|
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
|
|
|
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES=y
|
|
|
|
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
|
|
|
# end of Chipset
|
|
|
|
|
|
|
|
#
|
|
|
|
# Devices
|
|
|
|
#
|
|
|
|
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
|
|
|
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
|
|
|
CONFIG_HAVE_FSP_GOP=y
|
|
|
|
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
|
|
|
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
|
|
|
# CONFIG_VGA_ROM_RUN is not set
|
|
|
|
# CONFIG_RUN_FSP_GOP is not set
|
|
|
|
# CONFIG_NO_GFX_INIT is not set
|
|
|
|
CONFIG_NO_EARLY_GFX_INIT=y
|
|
|
|
|
|
|
|
#
|
|
|
|
# Display
|
|
|
|
#
|
|
|
|
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
2023-08-29 18:01:27 +00:00
|
|
|
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_LINEAR_FRAMEBUFFER=y
|
2023-12-15 16:33:27 +00:00
|
|
|
CONFIG_BOOTSPLASH=y
|
2023-12-15 16:27:05 +00:00
|
|
|
# end of Display
|
|
|
|
|
|
|
|
CONFIG_PCI=y
|
|
|
|
CONFIG_ECAM_MMCONF_SUPPORT=y
|
|
|
|
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_AZALIA_LOCK_DOWN_R_WO_GCAP=y
|
|
|
|
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
|
|
|
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
|
|
|
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
|
|
|
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
|
|
|
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
|
|
|
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
|
|
|
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
|
|
|
# CONFIG_EARLY_PCI_BRIDGE is not set
|
|
|
|
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
|
|
|
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
|
|
|
CONFIG_INTEL_GMA_HAVE_VBT=y
|
|
|
|
CONFIG_INTEL_GMA_ADD_VBT=y
|
|
|
|
# CONFIG_SOFTWARE_I2C is not set
|
|
|
|
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
|
|
|
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
|
|
|
# end of Devices
|
|
|
|
|
|
|
|
#
|
|
|
|
# Generic Drivers
|
|
|
|
#
|
|
|
|
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
|
|
|
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
|
|
|
# CONFIG_ELOG is not set
|
|
|
|
CONFIG_CACHE_MRC_SETTINGS=y
|
|
|
|
CONFIG_MRC_SETTINGS_PROTECT=y
|
|
|
|
# CONFIG_SMMSTORE is not set
|
|
|
|
CONFIG_SPI_FLASH=y
|
|
|
|
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
|
|
|
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
|
|
|
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
|
|
|
CONFIG_TPM_INIT_RAMSTAGE=y
|
|
|
|
# CONFIG_TPM_PPI is not set
|
|
|
|
CONFIG_NO_UART_ON_SUPERIO=y
|
|
|
|
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
|
|
|
# CONFIG_VPD is not set
|
|
|
|
CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
|
|
|
|
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
|
|
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
|
|
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
|
|
|
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
|
|
|
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
|
|
|
CONFIG_DRIVERS_I2C_GENERIC=y
|
|
|
|
CONFIG_DRIVERS_I2C_HID=y
|
|
|
|
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
|
|
|
CONFIG_HAVE_DPTF_EISA_HID=y
|
|
|
|
CONFIG_FSP_USE_REPO=y
|
|
|
|
# CONFIG_DISPLAY_HOBS is not set
|
|
|
|
# CONFIG_DISPLAY_UPD_DATA is not set
|
|
|
|
# CONFIG_BMP_LOGO is not set
|
|
|
|
CONFIG_PLATFORM_USES_FSP2_0=y
|
|
|
|
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
|
|
|
CONFIG_HAVE_INTEL_FSP_REPO=y
|
|
|
|
CONFIG_ADD_FSP_BINARIES=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_PLATFORM_USES_SECOND_FSP=y
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_FSP_T_LOCATION=0xfffe0000
|
|
|
|
CONFIG_FSP_S_CBFS="fsps.bin"
|
|
|
|
CONFIG_FSP_M_CBFS="fspm.bin"
|
|
|
|
CONFIG_FSP_FULL_FD=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_FSP_S_CBFS_2="fsps_2.bin"
|
|
|
|
CONFIG_FSP_M_CBFS_2="fspm_2.bin"
|
|
|
|
CONFIG_FSP_M_FILE_2="$(obj)/Fsp_2_M.fd"
|
|
|
|
CONFIG_FSP_S_FILE_2="$(obj)/Fsp_2_S.fd"
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
|
|
|
CONFIG_FSP_M_XIP=y
|
|
|
|
CONFIG_FSP_USES_CB_STACK=y
|
|
|
|
CONFIG_HAVE_FSP_LOGO_SUPPORT=y
|
|
|
|
CONFIG_FSP_COMPRESS_FSP_S_LZMA=y
|
|
|
|
CONFIG_FSP_STATUS_GLOBAL_RESET_REQUIRED_3=y
|
|
|
|
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
|
|
|
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
|
|
|
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
|
|
|
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
|
|
|
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
|
|
|
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
|
|
|
CONFIG_INTEL_GMA_ACPI=y
|
2023-10-11 13:06:06 +00:00
|
|
|
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
|
|
|
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
|
|
|
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
|
|
|
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_GFX_GMA=y
|
|
|
|
CONFIG_GFX_GMA_DYN_CPU=y
|
|
|
|
CONFIG_GFX_GMA_GENERATION="Skylake"
|
|
|
|
CONFIG_GFX_GMA_PCH="Cannon_Point"
|
|
|
|
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
|
|
|
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
|
|
|
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
|
|
|
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
|
|
|
CONFIG_DRIVERS_MC146818=y
|
|
|
|
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
|
|
|
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
|
|
|
CONFIG_MEMORY_MAPPED_TPM=y
|
|
|
|
CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
|
|
|
|
# CONFIG_DRIVERS_SIL_3114 is not set
|
|
|
|
CONFIG_DRIVERS_USB_ACPI=y
|
|
|
|
CONFIG_DRIVERS_WIFI_GENERIC=y
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
|
|
|
CONFIG_DRIVERS_MTK_WIFI=y
|
2023-12-15 16:27:05 +00:00
|
|
|
# end of Generic Drivers
|
|
|
|
|
|
|
|
#
|
|
|
|
# Security
|
|
|
|
#
|
|
|
|
|
|
|
|
#
|
|
|
|
# CBFS verification
|
|
|
|
#
|
|
|
|
# CONFIG_CBFS_VERIFICATION is not set
|
|
|
|
# end of CBFS verification
|
|
|
|
|
|
|
|
#
|
|
|
|
# Verified Boot (vboot)
|
|
|
|
#
|
|
|
|
CONFIG_VBOOT_LIB=y
|
|
|
|
# end of Verified Boot (vboot)
|
|
|
|
|
|
|
|
#
|
|
|
|
# Trusted Platform Module
|
|
|
|
#
|
|
|
|
# CONFIG_NO_TPM is not set
|
|
|
|
CONFIG_TPM1=y
|
|
|
|
CONFIG_TPM=y
|
|
|
|
CONFIG_MAINBOARD_HAS_TPM1=y
|
|
|
|
# CONFIG_TPM_DEACTIVATE is not set
|
|
|
|
# CONFIG_DEBUG_TPM is not set
|
|
|
|
# CONFIG_TPM_RDRESP_NEED_DELAY is not set
|
|
|
|
# CONFIG_TPM_LOG_CB is not set
|
|
|
|
CONFIG_TPM_LOG_TPM1=y
|
|
|
|
CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA=""
|
|
|
|
CONFIG_PCR_BOOT_MODE=1
|
|
|
|
CONFIG_PCR_HWID=1
|
|
|
|
CONFIG_PCR_SRTM=2
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
|
|
|
CONFIG_PCR_FW_VER=10
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_PCR_RUNTIME_DATA=3
|
|
|
|
# end of Trusted Platform Module
|
|
|
|
|
|
|
|
#
|
|
|
|
# Memory initialization
|
|
|
|
#
|
|
|
|
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
|
|
|
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
|
|
|
# end of Memory initialization
|
|
|
|
|
|
|
|
# CONFIG_INTEL_TXT is not set
|
|
|
|
# CONFIG_STM is not set
|
|
|
|
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
|
|
|
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
|
|
|
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
|
|
|
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
|
|
|
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
|
|
|
# end of Security
|
|
|
|
|
|
|
|
CONFIG_ACPI_HAVE_PCAT_8259=y
|
|
|
|
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
|
|
|
CONFIG_ACPI_SOC_NVS=y
|
|
|
|
CONFIG_ACPI_CUSTOM_MADT=y
|
|
|
|
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
|
|
|
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
|
|
|
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
|
|
|
CONFIG_HAVE_ACPI_TABLES=y
|
|
|
|
CONFIG_ACPI_LPIT=y
|
|
|
|
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
|
|
|
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
|
|
|
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
|
|
|
CONFIG_RTC=y
|
modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
|
|
|
CONFIG_HEAP_SIZE=0x100000
|
2023-12-15 16:27:05 +00:00
|
|
|
|
|
|
|
#
|
|
|
|
# Console
|
|
|
|
#
|
|
|
|
CONFIG_BOOTBLOCK_CONSOLE=y
|
|
|
|
CONFIG_POSTCAR_CONSOLE=y
|
|
|
|
CONFIG_SQUELCH_EARLY_SMP=y
|
|
|
|
# CONFIG_SPKMODEM is not set
|
|
|
|
# CONFIG_CONSOLE_NE2K is not set
|
|
|
|
CONFIG_CONSOLE_CBMEM=y
|
|
|
|
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
|
|
|
# CONFIG_CONSOLE_SPI_FLASH is not set
|
|
|
|
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
|
|
|
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
|
|
|
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
|
|
|
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
|
|
|
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
|
|
|
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
|
|
|
CONFIG_HWBASE_DEBUG_CB=y
|
|
|
|
# end of Console
|
|
|
|
|
|
|
|
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
|
|
|
CONFIG_HAVE_ACPI_RESUME=y
|
|
|
|
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
|
|
|
CONFIG_HAVE_MONOTONIC_TIMER=y
|
|
|
|
CONFIG_IOAPIC=y
|
|
|
|
CONFIG_ACPI_NHLT=y
|
|
|
|
|
|
|
|
#
|
|
|
|
# System tables
|
|
|
|
#
|
|
|
|
CONFIG_GENERATE_SMBIOS_TABLES=y
|
|
|
|
CONFIG_BIOS_VENDOR="coreboot"
|
|
|
|
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
|
|
|
# end of System tables
|
|
|
|
|
|
|
|
#
|
|
|
|
# Payload
|
|
|
|
#
|
|
|
|
# CONFIG_PAYLOAD_NONE is not set
|
|
|
|
# CONFIG_PAYLOAD_ELF is not set
|
|
|
|
# CONFIG_PAYLOAD_BOOTBOOT is not set
|
|
|
|
# CONFIG_PAYLOAD_FILO is not set
|
|
|
|
# CONFIG_PAYLOAD_GRUB2 is not set
|
|
|
|
# CONFIG_PAYLOAD_SEAGRUB is not set
|
|
|
|
# CONFIG_PAYLOAD_LINUXBOOT is not set
|
|
|
|
# CONFIG_PAYLOAD_SEABIOS is not set
|
|
|
|
# CONFIG_PAYLOAD_UBOOT is not set
|
|
|
|
# CONFIG_PAYLOAD_EDK2 is not set
|
2020-12-04 18:46:03 +00:00
|
|
|
CONFIG_PAYLOAD_LINUX=y
|
2022-08-16 16:39:33 +00:00
|
|
|
CONFIG_PAYLOAD_FILE="@BOARD_BUILD_DIR@/bzImage"
|
2023-12-15 16:27:05 +00:00
|
|
|
CONFIG_PAYLOAD_OPTIONS=""
|
|
|
|
# CONFIG_PXE is not set
|
2022-08-16 16:39:33 +00:00
|
|
|
CONFIG_LINUX_INITRD="@BOARD_BUILD_DIR@/initrd.cpio.xz"
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modules/coreboot: 24.02.01-Purism-1, remove CFLAGS overrides, needs nss
Update Purism coreboot to 24.02.01-Purism-1.
Remove CFLAGS overrides when building coreboot. These overrides break
24.02.01, which added (and needs) --param=min-pagesize=1024. This has
happened repeatedly in the past since Heads has to duplicate coreboot's
CFLAGS if it overrides them.
Specifically, the build fails with this error:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 1 is outside array bounds of 'void[0]' [-Werror=array-bounds=]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
In function 'setup_default_ebda':
cc1: note: source object is likely at address zero
That's because coreboot is attempting to write to EBDA at physical
address 0x40e, just above 1024. That is a valid address for x86, but
it's too close to 0 by default for GCC, --param-min-pagesize=1024
allows writes to physical addresses above 1024.
coreboot shouldn't need any of the usual Heads CFLAGS overrides for
reproducibility; it is already reproducible.
Fix indentation in modules/coreboot. Make accepted it before because
the indented lines followed a variable assignment, so they couldn't
be part of a recipe. That assignment is now gone, so they're now
interprted as part of a recipe for the `.configured` target just above,
they should not be indented.
Add nss to flake.nix, needed as of 24.02.01.
Update Librem coreboot configs for 24.02.01-Purism-1. Notably, the
board Kconfig changed for Mini v2 in coreboot, so this is needed for
correct builds.
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-18 20:42:31 +00:00
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# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
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2023-12-15 16:27:05 +00:00
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CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
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#
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# Secondary Payloads
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#
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# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
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# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
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# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
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# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set
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# CONFIG_TINT_SECONDARY_PAYLOAD is not set
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# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set
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# end of Secondary Payloads
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# end of Payload
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#
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# Debugging
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#
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#
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# CPU Debug Settings
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#
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# CONFIG_DISPLAY_MTRRS is not set
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2023-10-11 13:06:06 +00:00
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#
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# Vendorcode Debug Settings
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#
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2023-12-15 16:27:05 +00:00
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#
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# BLOB Debug Settings
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#
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# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
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# CONFIG_DISPLAY_FSP_HEADER is not set
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# CONFIG_VERIFY_HOBS is not set
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CONFIG_DISPLAY_FSP_VERSION_INFO=y
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CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
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# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
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#
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# General Debug Settings
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#
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# CONFIG_FATAL_ASSERTS is not set
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CONFIG_HAVE_DEBUG_GPIO=y
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# CONFIG_DEBUG_GPIO is not set
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# CONFIG_DEBUG_CBFS is not set
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CONFIG_HAVE_DEBUG_SMBUS=y
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# CONFIG_DEBUG_SMBUS is not set
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# CONFIG_DEBUG_MALLOC is not set
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# CONFIG_DEBUG_CONSOLE_INIT is not set
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# CONFIG_DEBUG_SPI_FLASH is not set
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# CONFIG_DEBUG_BOOT_STATE is not set
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# CONFIG_DEBUG_ADA_CODE is not set
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CONFIG_HAVE_EM100_SUPPORT=y
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# CONFIG_EM100 is not set
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# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
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# end of Debugging
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CONFIG_RAMSTAGE_ADA=y
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CONFIG_RAMSTAGE_LIBHWBASE=y
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CONFIG_SPD_READ_BY_WORD=y
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CONFIG_SPD_CACHE_IN_FMAP=y
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CONFIG_SPD_CACHE_FMAP_NAME="RW_SPD_CACHE"
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CONFIG_HWBASE_DYNAMIC_MMIO=y
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CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
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CONFIG_HWBASE_DIRECT_PCIDEV=y
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CONFIG_DECOMPRESS_OFAST=y
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CONFIG_WARNINGS_ARE_ERRORS=y
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CONFIG_MAX_REBOOT_CNT=3
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CONFIG_RELOCATABLE_MODULES=y
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CONFIG_GENERIC_GPIO_LIB=y
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CONFIG_HAVE_BOOTBLOCK=y
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CONFIG_HAVE_ROMSTAGE=y
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CONFIG_HAVE_RAMSTAGE=y
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