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48 lines
2.1 KiB
Diff
48 lines
2.1 KiB
Diff
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From cda3f1eb067e07e4a7110ef482912273d690be9e Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@puri.sm>
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Date: Tue, 25 Jan 2022 12:16:44 -0600
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Subject: [PATCH 5/9] soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master]
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updated the FSP binaries/headers for Comet Lake, which included a change
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moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing
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UDP in FSP-S was left in and deprecated, which allowed the change to go
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unnoticed until it was discovered that hotplug wasn't working.
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Since other related platforms (WHL, CFL) share the SoC code but use
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different FSP packages, add the setting of the PcieRpHotPlug UPD to
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romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'.
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Test: build/boot Purism Librem 14, verify WiFi killswitch operates
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as expected / WiFi is re-enabled when turning switch to on position.
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Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13
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Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
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Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377
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Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Reviewed-by: Nico Huber <nico.h@gmx.de>
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---
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src/soc/intel/cannonlake/romstage/fsp_params.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
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index 8cb6c92a65..0b63bd52f9 100644
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--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
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+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
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@@ -59,6 +59,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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m_cfg->EnableC6Dram = config->enable_c6dram;
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#if CONFIG(SOC_INTEL_COMETLAKE)
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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+ memcpy(tconfig->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(tconfig->PcieRpHotPlug));
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#else
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m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
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#endif
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--
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2.30.2
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