heads/patches/coreboot-4.11/0076-northbridge-amd-Added-resets-for-ram-training-failur.patch

From ce1c7a35fa11b46d0478e97c4a4001179ab9d1bf Mon Sep 17 00:00:00 2001
From: Mike Rothfuss <6182328+mrothfuss@users.noreply.github.com>
Date: Fri, 23 Aug 2024 19:59:09 -0600
Subject: [PATCH 2/2] northbridge/amd: Added resets for ram training failures

Instead of booting into an unstable state (and crashing), the board
resets to re-attempt raminit.
---
 src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 7 +++++--
 src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c
index 1ee10608b9..9a53bd352d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c
@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <string.h>
+#include <southbridge/amd/common/reset.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 
@@ -265,11 +266,13 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat,
 
 			pDCTstat->TargetFreq = final_target_freq;
 
-			if (global_phy_training_status)
+			if (global_phy_training_status) {
 				printk(BIOS_WARNING,
 					"%s: Uncorrectable invalid value(s) detected in second phase of write levelling; "
-					"continuing but system may be unstable!\n",
+					"Restarting system\n",
 					__func__);
+				soft_reset();
+			}
 
 			uint8_t dct;
 			for (dct = 0; dct < 2; dct++) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index dbb989fe3d..c4cb53442d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -26,6 +26,7 @@
 #include <string.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
+#include <southbridge/amd/common/reset.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 
@@ -1698,8 +1699,10 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 			Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000050, 0x13131313);
 		}
 		dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff;
-		if (dword)
-			printk(BIOS_ERR, "WARNING: MaxRdLatency training FAILED!  Attempting to continue but your system may be unstable...\n");
+		if (dword) {
+			printk(BIOS_ERR, "WARNING: MaxRdLatency training FAILED!  Restarting system\n");
+			soft_reset();
+		}
 
 		/* 2.10.5.8.5.1.5 */
 		nb_pstate = 0;
-- 
2.39.2