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40 lines
1.6 KiB
Diff
40 lines
1.6 KiB
Diff
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From bdaef1d8aa7cdfb27122665f951932e6e53d6a3d Mon Sep 17 00:00:00 2001
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From: Youness Alaoui <youness.alaoui@puri.sm>
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Date: Fri, 2 Mar 2018 17:03:11 -0500
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Subject: [PATCH 15/15] purism/librem_skl: Fix Librem 15 v3 devicetree
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configuration
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Recent changes to devicetree for librem_skl were only applied
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to the librem13v2 variant (Enable SpeedStep, VMX, TCC at 95C),
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this fixes it by applying the same fixes for the Librem 15 v3.
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Change-Id: I1d5c3ba844c942bd94311f4639612228ff8e07f8
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Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
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---
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.../purism/librem_skl/variants/librem15v3/devicetree.cb | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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index 6cf183a61f..035db18eff 100644
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--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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@@ -7,6 +7,15 @@ chip soc/intel/skylake
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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+ register "eist_enable" = "1"
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+ register "VmxEnable" = "1"
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+
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+ # Set the Thermal Control Circuit (TCC) activaction value to 95C
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+ # even though FSP integration guide says to set it to 100C for SKL-U
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+ # (offset at 0), because when the TCC activates at 100C, the CPU
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+ # will have already shut itself down from overheating protection.
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+ register "tcc_offset" = "5" # TCC of 95C
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+
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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--
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2.14.3
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