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https://github.com/genodelabs/genode.git
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5e5fe7291a
The commit adds support to throttle the rate of the RX IRQs to a specified value. The effect is, that no RX IRQs below the time threshold will fire and therefore the CPU load gets reduced on the host. Trade-off gaming between cpu load, throughput, overload. Modular Sculpt 23.10 on S938 as testcase. In brackets the CPU affinity is denoted. ipxe (0,0) -> nic_router (1,0) -> Debian VM vbox6 (3,0) and (3,1) VM: iperf -C X.X.X.X -t 60 -R iperf server X.X.X.X is outside Sculpt and sends data due to '-R' to VM Non representative measure points: cpu load - ipxe - nic_router - iperf throughput -------------------------------------------------- w/o patch - ~80% - ~50% - ~706 MBit/s - 0 -> throttling off by default on S938 patch 651 - ~20% - ~35% - ~763 MBit/s - 651 -> 0.166ms throttle RX IRQ patch 5580 - ~15% - ~25% - ~650 MBit/s - 5580 -> 1.4ms throttle RX IRQ Issue #5149
43 lines
1.2 KiB
Diff
43 lines
1.2 KiB
Diff
--- a/src/drivers/net/intel.c
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+++ b/src/drivers/net/intel.c
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@@ -681,6 +681,27 @@
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intel->force_icr = INTEL_IRQ_RXT0;
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}
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+ /*
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+ * Intel PCI/PCI-X family of Gigabit Ethernet control Software Developers's
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+ * Manual Rev 4.0
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+ *
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+ * 13.4.18 Interrupt Throttling Register
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+ * advises - 651 to 5580 - for "optimal performance setting"
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+ */
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+
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+ uint32_t const throttle_before = readl ( intel->regs + INTEL_ITR );
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+ uint32_t const throttle = 651; /* 651 * 256µs -> 0.166 ms */
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+
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+ writel( throttle, intel->regs + INTEL_ITR );
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+
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+ uint64_t const value = readl ( intel->regs + INTEL_ITR );
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+
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+ dde_printf("throttle RX interrupt %luµs%s -> %luµs - %s\n",
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+ 256ul * throttle_before / 1000ul,
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+ throttle_before ? "" : "(off)",
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+ 256ul * value / 1000ul,
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+ value == throttle ? "succeeded" : "failed");
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+
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return 0;
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intel_destroy_ring ( intel, &intel->rx );
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--- a/src/drivers/net/intel.h
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+++ b/src/drivers/net/intel.h
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@@ -102,6 +102,9 @@
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#define INTEL_IRQ_RXO 0x00000040UL /**< Receive overrun */
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#define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
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+/** Interrupt throttling Register */
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+#define INTEL_ITR 0x000C4UL
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+
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/** Interrupt Mask Set/Read Register */
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#define INTEL_IMS 0x000d0UL
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