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e70c13ce1f
- adds general support for semaphore timeouts - fixes PCID feature (aka tagged TLB) seeen on Lenovo X201 Fixes #1211
589 lines
14 KiB
C++
589 lines
14 KiB
C++
/*
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* \brief Syscall bindings for the NOVA microhypervisor
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* \author Norman Feske
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* \author Sebastian Sumpf
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* \author Alexander Boettcher
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* \date 2009-12-27
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*/
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/*
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* Copyright (c) 2009 Genode Labs
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _PLATFORM__NOVA_SYSCALLS_GENERIC_H_
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#define _PLATFORM__NOVA_SYSCALLS_GENERIC_H_
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#include <nova/stdint.h>
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namespace Nova {
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enum {
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PAGE_SIZE_LOG2 = 12,
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PAGE_SIZE_BYTE = 1 << PAGE_SIZE_LOG2,
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PAGE_MASK_ = ~(PAGE_SIZE_BYTE - 1)
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};
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/**
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* NOVA system-call IDs
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*/
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enum Syscall {
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NOVA_CALL = 0x0,
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NOVA_REPLY = 0x1,
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NOVA_CREATE_PD = 0x2,
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NOVA_CREATE_EC = 0x3,
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NOVA_CREATE_SC = 0x4,
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NOVA_CREATE_PT = 0x5,
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NOVA_CREATE_SM = 0x6,
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NOVA_REVOKE = 0x7,
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NOVA_LOOKUP = 0x8,
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NOVA_EC_CTRL = 0x9,
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NOVA_SC_CTRL = 0xa,
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NOVA_PT_CTRL = 0xb,
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NOVA_SM_CTRL = 0xc,
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NOVA_ASSIGN_PCI = 0xd,
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NOVA_ASSIGN_GSI = 0xe,
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};
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/**
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* NOVA status codes returned by system-calls
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*/
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enum Status
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{
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NOVA_OK = 0,
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NOVA_TIMEOUT = 1,
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NOVA_IPC_ABORT = 2,
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NOVA_INV_HYPERCALL = 3,
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NOVA_INV_SELECTOR = 4,
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NOVA_INV_PARAMETER = 5,
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NOVA_INV_FEATURE = 6,
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NOVA_INV_CPU = 7,
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NOVA_INVD_DEVICE_ID = 8,
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};
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/**
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* Hypervisor information page
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*/
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struct Hip
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{
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struct Mem_desc
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{
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enum Type {
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MULTIBOOT_MODULE = -2,
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MICROHYPERVISOR = -1,
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AVAILABLE_MEMORY = 1,
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RESERVED_MEMORY = 2,
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ACPI_RECLAIM_MEMORY = 3,
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ACPI_NVS_MEMORY = 4
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};
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uint64_t const addr;
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uint64_t const size;
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Type const type;
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uint32_t const aux;
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};
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uint32_t const signature; /* magic value 0x41564f4e */
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uint16_t const hip_checksum;
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uint16_t const hip_length;
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uint16_t const cpu_desc_offset;
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uint16_t const cpu_desc_size;
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uint16_t const mem_desc_offset;
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uint16_t const mem_desc_size;
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uint32_t const feature_flags;
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uint32_t const api_version;
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uint32_t const sel; /* number of cap selectors */
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uint32_t const sel_exc; /* number of cap selectors for exceptions */
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uint32_t const sel_vm; /* number of cap selectors for VM handling */
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uint32_t const sel_gsi; /* number of global system interrupts */
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uint32_t const page_sizes; /* supported page sizes */
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uint32_t const utcb_sizes; /* supported utcb sizes */
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uint32_t const tsc_freq; /* time-stamp counter frequency in kHz */
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uint32_t const bus_freq; /* bus frequency in kHz */
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bool has_feature_vmx() const { return feature_flags & (1 << 1); }
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bool has_feature_svm() const { return feature_flags & (1 << 2); }
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unsigned cpu_max() const {
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return (mem_desc_offset - cpu_desc_offset) / cpu_desc_size; }
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unsigned cpus() const {
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unsigned cpu_num = 0;
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const char * cpu_desc =
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reinterpret_cast<const char *>(this) + cpu_desc_offset;
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for (unsigned i = 0; i < cpu_max(); i++) {
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if ((*cpu_desc) & 0x1) cpu_num++;
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cpu_desc += cpu_desc_size;
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}
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return cpu_num;
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}
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} __attribute__((packed));
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/**
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* Semaphore operations
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*/
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enum Sem_op { SEMAPHORE_UP = 0U, SEMAPHORE_DOWN = 1U, SEMAPHORE_DOWNZERO = 0x3U };
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/**
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* Ec operations
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*/
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enum Ec_op { EC_RECALL = 0U, EC_YIELD = 1U, EC_DONATE_SC = 2U, EC_RESCHEDULE = 3U };
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class Descriptor
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{
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protected:
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mword_t _value;
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/**
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* Assign bitfield to descriptor
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*/
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template<mword_t MASK, mword_t SHIFT>
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void _assign(mword_t new_bits)
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{
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_value &= ~(MASK << SHIFT);
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_value |= (new_bits & MASK) << SHIFT;
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}
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/**
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* Query bitfield from descriptor
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*/
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template<mword_t MASK, mword_t SHIFT>
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mword_t _query() const { return (_value >> SHIFT) & MASK; }
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public:
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mword_t value() const { return _value; }
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} __attribute__((packed));
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/**
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* Message-transfer descriptor
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*/
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class Mtd
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{
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private:
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mword_t const _value;
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public:
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enum {
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ACDB = 1U << 0, /* eax, ecx, edx, ebx */
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EBSD = 1U << 1, /* ebp, esi, edi */
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ESP = 1U << 2,
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EIP = 1U << 3,
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EFL = 1U << 4, /* eflags */
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ESDS = 1U << 5,
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FSGS = 1U << 6,
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CSSS = 1U << 7,
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TR = 1U << 8,
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LDTR = 1U << 9,
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GDTR = 1U << 10,
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IDTR = 1U << 11,
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CR = 1U << 12,
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DR = 1U << 13, /* DR7 */
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SYS = 1U << 14, /* Sysenter MSRs CS, ESP, EIP */
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QUAL = 1U << 15, /* exit qualification */
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CTRL = 1U << 16, /* execution controls */
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INJ = 1U << 17, /* injection info */
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STA = 1U << 18, /* interruptibility state */
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TSC = 1U << 19, /* time-stamp counter */
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EFER = 1U << 20, /* EFER MSR */
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FPU = 1U << 31, /* FPU state */
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IRQ = EFL | STA | INJ | TSC,
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ALL = 0x000fffff & ~CTRL,
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};
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Mtd(mword_t value) : _value(value) { }
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mword_t value() const { return _value; }
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};
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class Crd : public Descriptor
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{
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protected:
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/**
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* Bitfield holding the descriptor type
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*/
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enum {
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TYPE_MASK = 0x3, TYPE_SHIFT = 0,
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BASE_SHIFT = 12, RIGHTS_MASK = 0x1f,
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ORDER_MASK = 0x1f, ORDER_SHIFT = 7,
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BASE_MASK = (~0UL) >> BASE_SHIFT,
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RIGHTS_SHIFT= 2
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};
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/**
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* Capability-range-descriptor types
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*/
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enum {
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NULL_CRD_TYPE = 0,
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MEM_CRD_TYPE = 1,
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IO_CRD_TYPE = 2,
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OBJ_CRD_TYPE = 3,
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RIGHTS_ALL = 0x1f,
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};
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void _base(mword_t base)
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{ _assign<BASE_MASK, BASE_SHIFT>(base); }
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void _order(mword_t order)
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{ _assign<ORDER_MASK, ORDER_SHIFT>(order); }
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public:
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Crd(mword_t base, mword_t order) {
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_value = 0; _base(base), _order(order); }
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Crd(mword_t value) { _value = value; }
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mword_t hotspot(mword_t sel_hotspot) const
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{
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if ((value() & TYPE_MASK) == MEM_CRD_TYPE)
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return sel_hotspot & PAGE_MASK_;
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return sel_hotspot << 12;
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}
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mword_t addr() const { return base() << BASE_SHIFT; }
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mword_t base() const { return _query<BASE_MASK, BASE_SHIFT>(); }
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mword_t order() const { return _query<ORDER_MASK, ORDER_SHIFT>(); }
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bool is_null() const { return (_value & TYPE_MASK) == NULL_CRD_TYPE; }
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uint8_t type() const { return _query<TYPE_MASK, TYPE_SHIFT>(); }
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uint8_t rights() const { return _query<RIGHTS_MASK, RIGHTS_SHIFT>(); }
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} __attribute__((packed));
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class Rights
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{
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private:
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bool const _readable, _writeable, _executable;
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public:
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Rights(bool readable, bool writeable, bool executable)
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: _readable(readable), _writeable(writeable),
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_executable(executable) { }
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Rights() : _readable(false), _writeable(false), _executable(false) {}
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bool readable() const { return _readable; }
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bool writeable() const { return _writeable; }
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bool executable() const { return _executable; }
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};
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/**
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* Memory-capability-range descriptor
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*/
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class Mem_crd : public Crd
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{
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private:
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enum {
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EXEC_MASK = 0x1, EXEC_SHIFT = 4,
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WRITE_MASK = 0x1, WRITE_SHIFT = 3,
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READ_MASK = 0x1, READ_SHIFT = 2
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};
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void _rights(Rights r)
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{
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_assign<EXEC_MASK, EXEC_SHIFT>(r.executable());
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_assign<WRITE_MASK, WRITE_SHIFT>(r.writeable());
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_assign<READ_MASK, READ_SHIFT>(r.readable());
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}
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public:
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Mem_crd(mword_t base, mword_t order, Rights rights = Rights())
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: Crd(base, order)
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{
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_rights(rights);
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_assign<TYPE_MASK, TYPE_SHIFT>(MEM_CRD_TYPE);
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}
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Rights rights() const
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{
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return Rights(_query<READ_MASK, READ_SHIFT>(),
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_query<WRITE_MASK, WRITE_SHIFT>(),
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_query<EXEC_MASK, EXEC_SHIFT>());
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}
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};
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/**
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* I/O-capability-range descriptor
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*/
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class Io_crd : public Crd
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{
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public:
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Io_crd(mword_t base, mword_t order)
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: Crd(base, order)
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{
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_assign<TYPE_MASK, TYPE_SHIFT>(IO_CRD_TYPE);
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_assign<RIGHTS_MASK, RIGHTS_SHIFT>(RIGHTS_ALL);
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}
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};
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class Obj_crd : public Crd
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{
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public:
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enum {
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RIGHT_EC_RECALL = 0x1U,
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RIGHT_PT_CALL = 0x1U,
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RIGHT_PT_CTRL = 0x2U,
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RIGHT_SM_UP = 0x1U,
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RIGHT_SM_DOWN = 0x2U
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};
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Obj_crd() : Crd(0, 0)
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{
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_assign<TYPE_MASK, TYPE_SHIFT>(NULL_CRD_TYPE);
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}
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Obj_crd(mword_t base, mword_t order,
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mword_t rights = RIGHTS_ALL)
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: Crd(base, order)
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{
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_assign<TYPE_MASK, TYPE_SHIFT>(OBJ_CRD_TYPE);
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_assign<RIGHTS_MASK, RIGHTS_SHIFT>(rights);
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}
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};
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/**
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* Quantum-priority descriptor
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*/
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class Qpd : public Descriptor
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{
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private:
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enum {
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PRIORITY_MASK = 0xff, PRIORITY_SHIFT = 0,
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QUANTUM_SHIFT = 12,
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QUANTUM_MASK = (~0UL) >> QUANTUM_SHIFT
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};
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void _quantum(mword_t quantum)
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{ _assign<QUANTUM_MASK, QUANTUM_SHIFT>(quantum); }
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void _priority(mword_t priority)
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{ _assign<PRIORITY_MASK, PRIORITY_SHIFT>(priority); }
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public:
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enum { DEFAULT_QUANTUM = 10000, DEFAULT_PRIORITY = 64 };
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Qpd(mword_t quantum = DEFAULT_QUANTUM,
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mword_t priority = DEFAULT_PRIORITY)
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{
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_value = 0;
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_quantum(quantum), _priority(priority);
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}
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mword_t quantum() const { return _query<QUANTUM_MASK, QUANTUM_SHIFT>(); }
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mword_t priority() const { return _query<PRIORITY_MASK, PRIORITY_SHIFT>(); }
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};
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/**
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* User-level thread-control block
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*/
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struct Utcb
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{
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/**
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* Number of untyped items uses lowest 16 bit, number of typed items
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* uses bit 16-31, bit 32+ are ignored on 64bit
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*/
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mword_t items;
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Crd crd_xlt; /* receive capability-range descriptor for translation */
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Crd crd_rcv; /* receive capability-range descriptor for delegation */
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mword_t tls;
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/**
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* Data area
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*
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* The UTCB entries following the header hold message payload (normal
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* IDC operations) or architectural state (exception handling).
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*/
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union {
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/* message payload */
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mword_t msg[];
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/* exception state */
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struct {
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mword_t mtd, instr_len, ip, flags;
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unsigned intr_state, actv_state, inj_info, inj_error;
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mword_t ax, cx, dx, bx;
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mword_t sp, bp, si, di;
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#ifdef __x86_64__
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mword_t r8, r9, r10, r11, r12, r13, r14, r15;
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#endif
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unsigned long long qual[2]; /* exit qualification */
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unsigned ctrl[2];
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unsigned long long reserved;
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mword_t cr0, cr2, cr3, cr4;
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#ifdef __x86_64__
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mword_t cr8, efer;
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#endif
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mword_t dr7, sysenter_cs, sysenter_sp, sysenter_ip;
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struct {
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unsigned short sel, ar;
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unsigned limit;
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mword_t base;
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#ifndef __x86_64__
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mword_t reserved;
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#endif
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} es, cs, ss, ds, fs, gs, ldtr, tr;
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struct {
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unsigned reserved0;
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unsigned limit;
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mword_t base;
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#ifndef __x86_64__
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mword_t reserved1;
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#endif
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} gdtr, idtr;
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unsigned long long tsc_val, tsc_off;
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} __attribute__((packed));
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};
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struct Item {
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mword_t crd;
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mword_t hotspot;
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bool is_del() { return hotspot & 0x1; }
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};
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/**
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* Set number of untyped message words
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*
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* Calling this function has the side effect of removing all typed
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* message items from the message buffer.
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*/
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void set_msg_word(unsigned num) { items = num; }
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/**
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* Return current number of message word in UTCB
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*/
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unsigned msg_words() { return items & 0xffffU; }
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/**
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* Return current number of message items on UTCB
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*/
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unsigned msg_items() { return items >> 16; }
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/**
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* Append message-transfer item to message buffer
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*
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* \param exception true to append the item to an exception reply
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*/
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__attribute__((warn_unused_result))
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bool append_item(Crd crd, mword_t sel_hotspot,
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bool kern_pd = false,
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bool update_guest_pt = false,
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bool translate_map = false,
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bool dma_mem = false)
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{
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/* transfer items start at the end of the UTCB */
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items += 1 << 16;
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Item *item = reinterpret_cast<Item *>(this);
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item += (PAGE_SIZE_BYTE / sizeof(struct Item)) - msg_items();
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/* check that there is enough space left on UTCB */
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if (msg + msg_words() >= reinterpret_cast<mword_t *>(item)) {
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items -= 1 << 16;
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return false;
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}
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/* map from hypervisor or current pd */
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unsigned h = kern_pd ? (1 << 11) : 0;
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/* update guest page table */
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unsigned g = update_guest_pt ? (1 << 10) : 0;
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/* mark memory dma able */
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unsigned d = dma_mem ? (1 << 9) : 0;
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/* set type of delegation, either 'map' or 'translate and map' */
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unsigned m = translate_map ? 2 : 1;
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item->hotspot = crd.hotspot(sel_hotspot) | g | h | d | m;
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item->crd = crd.value();
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return true;
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}
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|
|
|
/**
|
|
* Return typed item at postion i in UTCB
|
|
*
|
|
* \param i position of item requested, starts with 0
|
|
*/
|
|
Item * get_item(const unsigned i) {
|
|
if (i > (PAGE_SIZE_BYTE / sizeof(struct Item))) return 0;
|
|
Item * item = reinterpret_cast<Item *>(this) + (PAGE_SIZE_BYTE / sizeof(struct Item)) - i - 1;
|
|
if (reinterpret_cast<mword_t *>(item) < this->msg) return 0;
|
|
return item;
|
|
}
|
|
|
|
mword_t mtd_value() const { return static_cast<Mtd>(mtd).value(); }
|
|
} __attribute__((packed));
|
|
|
|
/**
|
|
* Size of event-specific portal window mapped at PD creation time
|
|
*/
|
|
enum {
|
|
NUM_INITIAL_PT_LOG2 = 5,
|
|
NUM_INITIAL_PT = 1UL << NUM_INITIAL_PT_LOG2,
|
|
NUM_INITIAL_PT_RESERVED = 2 * NUM_INITIAL_PT,
|
|
NUM_INITIAL_VCPU_PT_LOG2 = 8,
|
|
};
|
|
|
|
/**
|
|
* Event-specific capability selectors
|
|
*/
|
|
enum {
|
|
PT_SEL_PAGE_FAULT = 0xe,
|
|
PT_SEL_PARENT = 0x1a, /* convention on Genode */
|
|
PT_SEL_MAIN_PAGER = 0x1b, /* convention on Genode */
|
|
PT_SEL_MAIN_EC = 0x1c, /* convention on Genode */
|
|
PT_SEL_STARTUP = 0x1e,
|
|
PT_SEL_RECALL = 0x1f,
|
|
SM_SEL_EC = 0x1d, /* convention on Genode */
|
|
};
|
|
|
|
}
|
|
#endif /* _PLATFORM__NOVA_SYSCALLS_GENERIC_H_ */
|