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6d48b5484d
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685
87 lines
1.7 KiB
C++
87 lines
1.7 KiB
C++
/*
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* \brief MMIO and IRQ definitions common to Exynos5 SoC
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* \author Stefan Kalkowski
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* \date 2013-11-25
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <drivers/defs/arm_v7.h>
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#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
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#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
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namespace Exynos5 {
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using namespace Arm_v7;
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enum {
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/* normal RAM */
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RAM_0_BASE = 0x40000000,
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RAM_0_SIZE = 0x80000000,
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/* device IO memory */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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/* interrupt controller */
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IRQ_CONTROLLER_BASE = 0x10480000,
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IRQ_CONTROLLER_SIZE = 0x00010000,
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IRQ_CONTROLLER_VT_CTRL_BASE = 0x10484000,
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IRQ_CONTROLLER_VT_CTRL_SIZE = 0x1000,
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IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
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IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
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/* UART */
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UART_2_MMIO_BASE = 0x12C20000,
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UART_2_MMIO_SIZE = 0x1000,
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UART_2_IRQ = 85,
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/* pulse-width-modulation timer */
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PWM_MMIO_BASE = 0x12dd0000,
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PWM_MMIO_SIZE = 0x1000,
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PWM_CLOCK = 66000000,
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PWM_IRQ_0 = 68,
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/* multicore timer */
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MCT_MMIO_BASE = 0x101c0000,
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MCT_MMIO_SIZE = 0x1000,
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MCT_CLOCK = 24000000,
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MCT_IRQ_L0 = 152,
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MCT_IRQ_L1 = 153,
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/* IRAM */
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IRAM_BASE = 0x02020000,
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/* SATA/AHCI */
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SATA_IRQ = 147,
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/* SD card */
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SDMMC0_IRQ = 107,
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/******************************
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** HDMI memory map and irqs **
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******************************/
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/* Mixer base */
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MIXER_BASE = 0x14450000,
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/* HDMI base */
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HDMI_BASE = 0x14530000,
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/* I2C BASE */
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I2C_BASE = 0x12ce0000,
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/* I2C */
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I2C_HDMI_IRQ = 96,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_ */
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