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https://github.com/genodelabs/genode.git
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6d48b5484d
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685
97 lines
2.3 KiB
C++
97 lines
2.3 KiB
C++
/*
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* \brief MMIO and IRQ definitions for the OMAP4 PandaBoard revision A2
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__PANDA_H_
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#define _INCLUDE__DRIVERS__DEFS__PANDA_H_
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namespace Panda {
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enum {
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/* device IO memory */
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MMIO_0_BASE = 0x48000000,
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MMIO_0_SIZE = 0x01000000,
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MMIO_1_BASE = 0x4a000000,
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MMIO_1_SIZE = 0x01000000,
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/* normal RAM */
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RAM_0_BASE = 0x80000000,
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RAM_0_SIZE = 0x40000000,
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/* clocks */
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SYS_CLK = 38400000,
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/* UART controllers */
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TL16C750_1_MMIO_BASE = MMIO_0_BASE + 0x6a000,
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TL16C750_2_MMIO_BASE = MMIO_0_BASE + 0x6c000,
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TL16C750_3_MMIO_BASE = MMIO_0_BASE + 0x20000,
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TL16C750_4_MMIO_BASE = MMIO_0_BASE + 0x6e000,
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TL16C750_MMIO_SIZE = 0x2000,
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TL16C750_CLOCK = 48*1000*1000,
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TL16C750_1_IRQ = 104,
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TL16C750_2_IRQ = 105,
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TL16C750_3_IRQ = 106,
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TL16C750_4_IRQ = 102,
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/* USB */
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HSUSB_EHCI_IRQ = 109,
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/* timer modules */
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GP_TIMER_3_IRQ = 71,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x48240000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 400000000,
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CORTEX_A9_PRIVATE_TIMER_DIV = 200,
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CORTEX_A9_WUGEN_MMIO_BASE = 0x48281000,
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CORTEX_A9_SCU_MMIO_BASE = 0x48240000,
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/* L2 cache */
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PL310_MMIO_BASE = 0x48242000,
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PL310_MMIO_SIZE = 0x00001000,
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/* display subsystem */
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DSS_MMIO_BASE = 0x58000000,
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DSS_MMIO_SIZE = 0x00001000,
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DISPC_MMIO_BASE = 0x58001000,
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DISPC_MMIO_SIZE = 0x00001000,
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HDMI_MMIO_BASE = 0x58006000,
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HDMI_MMIO_SIZE = 0x00001000,
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/* GPIO */
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GPIO1_MMIO_BASE = 0x4a310000,
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GPIO1_MMIO_SIZE = 0x1000,
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GPIO1_IRQ = 29 + 32,
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GPIO2_MMIO_BASE = 0x48055000,
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GPIO2_MMIO_SIZE = 0x1000,
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GPIO2_IRQ = 30 + 32,
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GPIO3_MMIO_BASE = 0x48057000,
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GPIO3_MMIO_SIZE = 0x1000,
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GPIO3_IRQ = 31 + 32,
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GPIO4_MMIO_BASE = 0x48059000,
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GPIO4_MMIO_SIZE = 0x1000,
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GPIO4_IRQ = 32 + 32,
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GPIO5_MMIO_BASE = 0x4805b000,
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GPIO5_MMIO_SIZE = 0x1000,
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GPIO5_IRQ = 33 + 32,
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GPIO6_MMIO_BASE = 0x4805d000,
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GPIO6_MMIO_SIZE = 0x1000,
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GPIO6_IRQ = 34 + 32,
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/* SD card */
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HSMMC_IRQ = 115,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__PANDA_H_ */
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