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786fe805da
On ARM it's relevant to not only distinguish between ordinary cached memory and write-combined one, but also having non-cached memory too. To insert the appropriated page table entries e.g.: in the base-hw kernel, we need to preserve the information about the kind of memory from allocation until the pager resolves a page fault. Therefore, this commit introduces a new Cache_attribute type, and replaces the write_combined boolean with the new type where necessary.
202 lines
4.7 KiB
C++
202 lines
4.7 KiB
C++
/*
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* \brief Fiasco.OC pager support
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* \author Christian Helmuth
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* \author Stefan Kalkowski
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* \date 2006-06-14
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*/
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/*
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* Copyright (C) 2006-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__BASE__IPC_PAGER_H_
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#define _INCLUDE__BASE__IPC_PAGER_H_
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/* Genode includes */
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#include <base/cache.h>
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#include <base/ipc.h>
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#include <base/stdint.h>
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#include <base/native_types.h>
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#include <base/thread_state.h>
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#include <util/touch.h>
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/* Fiasco includes */
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namespace Fiasco {
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#include <l4/sys/types.h>
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}
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namespace Genode {
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class Mapping
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{
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private:
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addr_t _dst_addr;
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addr_t _src_addr;
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Cache_attribute _cacheability;
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bool _iomem;
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unsigned _log2size;
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bool _rw;
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bool _grant;
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public:
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/**
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* Constructor
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*/
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Mapping(addr_t dst_addr, addr_t src_addr,
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Cache_attribute c, bool io_mem,
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unsigned l2size = L4_LOG2_PAGESIZE,
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bool rw = true, bool grant = false)
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: _dst_addr(dst_addr), _src_addr(src_addr),
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_cacheability(c), _iomem(io_mem), _log2size(l2size),
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_rw(rw), _grant(grant) { }
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/**
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* Construct invalid flexpage
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*/
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Mapping() : _dst_addr(0), _src_addr(0), _cacheability(UNCACHED),
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_iomem(false), _log2size(0), _rw(false), _grant(false) { }
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Fiasco::l4_umword_t dst_addr() const { return _dst_addr; }
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bool grant() const { return _grant; }
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Fiasco::l4_fpage_t fpage() const
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{
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unsigned char rights = _rw ? Fiasco::L4_FPAGE_RWX : Fiasco::L4_FPAGE_RX;
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return Fiasco::l4_fpage(_src_addr, _log2size, rights);
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}
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Cache_attribute cacheability() const { return _cacheability; }
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bool iomem() { return _iomem; }
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/**
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* Prepare map operation is not needed on Fiasco.OC, since we clear the
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* dataspace before this function is called.
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*/
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void prepare_map_operation() { }
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};
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/**
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* Special paging server class
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*/
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class Ipc_pager : public Native_capability
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{
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public:
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enum Msg_type { PAGEFAULT, WAKE_UP, PAUSE, EXCEPTION };
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private:
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Native_thread _last; /* origin of last fault */
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addr_t _pf_addr; /* page-fault address */
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addr_t _pf_ip; /* ip of faulter */
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Mapping _reply_mapping; /* page-fault answer */
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unsigned long _badge; /* badge of faulting thread */
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Fiasco::l4_msgtag_t _tag; /* receive message tag */
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Fiasco::l4_exc_regs_t _regs; /* exception registers */
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Msg_type _type;
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void _parse_msg_type(void);
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void _parse_exception(void);
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void _parse_pagefault(void);
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void _parse(unsigned long label);
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public:
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/**
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* Constructor
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*/
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Ipc_pager();
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/**
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* Wait for a new page fault received as short message IPC
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*/
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void wait_for_fault();
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/**
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* Reply current page-fault and wait for a new one
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*
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* Send short flex page and wait for next short-message (register)
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* IPC -- pagefault
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*/
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void reply_and_wait_for_fault();
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/**
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* Request instruction pointer of current page fault
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*/
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addr_t fault_ip() { return _pf_ip; }
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/**
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* Request fault address of current page fault
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*/
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addr_t fault_addr() { return _pf_addr & ~3; }
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/**
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* Set parameters for next reply
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*/
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void set_reply_mapping(Mapping m) { _reply_mapping = m; }
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/**
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* Set destination for next reply
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*/
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void set_reply_dst(Native_thread t) {
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_last = t; }
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/**
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* Answer call without sending a flex-page mapping
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*
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* This function is used to acknowledge local calls from one of
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* core's region-manager sessions.
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*/
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void acknowledge_wakeup();
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/**
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* Reply to an exception IPC
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*/
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void acknowledge_exception();
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/**
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* Return thread ID of last faulter
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*/
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Native_thread last() const { return _last; }
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/**
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* Return badge for faulting thread
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*/
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unsigned long badge() { return _badge; }
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bool is_write_fault() const { return (_pf_addr & 2); }
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/**
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* Return true if last fault was an exception
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*/
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bool is_exception() const
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{
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return _type == Ipc_pager::EXCEPTION;
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}
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/**
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* Return the type of ipc we received at last.
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*/
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Msg_type msg_type() { return _type; };
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/**
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* Copy the exception registers from the last exception
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* to the given Thread_state object.
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*/
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void get_regs(Thread_state *state);
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/*
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* Copy the exception reply registers from the given
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* Thread_state object
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*/
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void set_regs(Thread_state state);
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};
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}
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#endif /* _INCLUDE__BASE__IPC_PAGER_H_ */
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