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d65beb970d
* enable i915 driver from Linux 3.14.5
* tested for generation 5 till 8 GPUs
The driver can be configured at run-time via the config ROM. Every
connector of the graphic card can be configured separately using the
following syntax
<config>
<connector name="LVDS-11" width="1280" height="800" enabled="true"/>
</config>
Also, when enabled within the intel framebuffer driver configuration like
the following
<config buffered="yes"/>
a simple ram dataspace is propagated to the client and the driver
itselfs copies from that buffer to the framebuffer triggered via refresh
calls. This option is useful to alleviate tearing effects.
The driver distributes all available connectors of the graphic card and
their supported resolutions via a report. It looks like follows
<connectors>
<connector name="LVDS-11" connected="1">
<mode width="1280" height="800" hz="60"/>
...
</connector>
...
</connectors>
The driver distributes the report only if this is stated within its
configuration, like the following
<config>
<report connectors="yes"/>
</config>
Fix #1764
56 lines
2.2 KiB
Diff
56 lines
2.2 KiB
Diff
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
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index 2688f6d..ca178a2 100644
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--- a/drivers/gpu/drm/i915/intel_dp.c
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+++ b/drivers/gpu/drm/i915/intel_dp.c
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@@ -811,7 +811,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc *intel_crtc = encoder->new_crtc;
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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int lane_count, clock;
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+ int min_lane_count = 1;
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int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
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+ int min_clock = 0;
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int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
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int bpp, mode_rate;
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static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
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@@ -844,19 +846,33 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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/* Walk through all bpp values. Luckily they're all nicely spaced with 2
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* bpc in between. */
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bpp = pipe_config->pipe_bpp;
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- if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
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- dev_priv->vbt.edp_bpp < bpp) {
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- DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
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- dev_priv->vbt.edp_bpp);
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- bpp = dev_priv->vbt.edp_bpp;
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+ if (is_edp(intel_dp)) {
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+ if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
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+ DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
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+ dev_priv->vbt.edp_bpp);
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+ bpp = dev_priv->vbt.edp_bpp;
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+ }
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+
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+ if (dev_priv->vbt.edp_lanes) {
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+ min_lane_count = min(dev_priv->vbt.edp_lanes,
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+ max_lane_count);
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+ DRM_DEBUG_KMS("using min %u lanes per VBT\n",
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+ min_lane_count);
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+ }
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+
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+ if (dev_priv->vbt.edp_rate) {
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+ min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
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+ DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
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+ bws[min_clock]);
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+ }
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}
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for (; bpp >= 6*3; bpp -= 2*3) {
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mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
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bpp);
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- for (clock = 0; clock <= max_clock; clock++) {
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- for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
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+ for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
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+ for (clock = min_clock; clock <= max_clock; clock++) {
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link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
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link_avail = intel_dp_max_data_rate(link_clock,
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lane_count);
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