Martin Stein 665a551fcd base-hw & cortex_a9: consider timer IRQ unreliable ... On some Cortex A9 platforms (Qemu 4.2.1 PBXA9), the IRQ status register is not reliable. Sometimes, it indicates an IRQ too early, i.e., shortly before the counter wraps. Therefore we have to accomplish wrap detection via counter comparison only. We check whether the current counter value is higher than the start counter value of the current timeout. However, this implies that we have to take care to always read out the counter before it hits the max timout value again. And, therefore, the max timeout value has to be far away from the first value the counter has after wrapping. Consequently, we propagate a max timeout value of half the max counter value. Fixes #4209		2022-10-12 12:09:34 +02:00
..
bootstrap	board: Rename virt_qemu to virt_qemu_<arch>	2022-08-17 12:03:26 +02:00
core	base-hw & cortex_a9: consider timer IRQ unreliable	2022-10-12 12:09:34 +02:00
include	base-hw: add bitfield to pl310	2022-04-13 08:08:01 +02:00
lib	Remove pseudo targets for building shared libs	2022-09-19 14:00:32 +02:00
test	base-hw: update cpu_scheduler unit test	2022-10-12 11:59:08 +02:00
timer/hw	base: avoid implicit conversions	2021-12-17 15:04:44 +01:00