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6d48b5484d
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685
81 lines
1.7 KiB
C++
81 lines
1.7 KiB
C++
/**
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* \brief MMIO and IRQ definitions for the Realview PBXA9 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__PBXA9_H_
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#define _INCLUDE__DRIVERS__DEFS__PBXA9_H_
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namespace Pbxa9 {
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enum {
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/* normal RAM */
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RAM_0_BASE = 0x70000000,
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RAM_0_SIZE = 0x20000000,
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RAM_1_BASE = 0x20000000,
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RAM_1_SIZE = 0x10000000,
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/* device IO memory */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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MMIO_1_BASE = 0x4e000000,
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MMIO_1_SIZE = 0x01000000,
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NORTHBRIDGE_AHB_BASE = 0x10020000,
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NORTHBRIDGE_AHB_SIZE = 768*1024,
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/* southbridge */
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SOUTHBRIDGE_APB_BASE = 0x10000000,
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SOUTHBRIDGE_APB_SIZE = 128*1024,
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/* clocks */
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OSC_6_CLOCK = 24*1000*1000,
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/* system controller */
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SYSTEM_CONTROL_MMIO_BASE = 0x10000000,
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/* CPU */
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CORTEX_A9_PRIVATE_TIMER_CLK = 100000000,
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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/* L2 cache controller */
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PL310_MMIO_BASE = 0x1f002000,
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PL310_MMIO_SIZE = 0x00001000,
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/* UART */
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PL011_0_MMIO_BASE = 0x10009000,
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PL011_0_MMIO_SIZE = 0x00001000,
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PL011_0_CLOCK = OSC_6_CLOCK,
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PL011_0_IRQ = 44,
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PL011_1_IRQ = 45,
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PL011_2_IRQ = 46,
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PL011_3_IRQ = 47,
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/* timer */
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SP804_0_1_MMIO_BASE = 0x10011000,
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SP804_0_1_MMIO_SIZE = 0x00001000,
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SP804_0_1_IRQ = 36,
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SP804_0_1_CLOCK = 1000*1000,
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/* keyboard & mouse */
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KMI_0_IRQ = 52,
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KMI_1_IRQ = 53,
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/* SD card */
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PL180_IRQ_0 = 49,
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PL180_IRQ_1 = 50,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__PBXA9_H_ */
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