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4e97a6511b
* Instead of always re-load page-tables when a thread context is switched only do this when another user PD's thread is the next target, core-threads are always executed within the last PD's page-table set * remove the concept of the mode transition * instead map the exception vector once in bootstrap code into kernel's memory segment * when a new page directory is constructed for a user PD, copy over the top-level kernel segment entries on RISCV and X86, on ARM we use a designated page directory register for the kernel segment * transfer the current CPU id from bootstrap to core/kernel in a register to ease first stack address calculation * align cpu context member of threads and vms, because of x86 constraints regarding the stack-pointer loading * introduce Align_at template for members with alignment constraints * let the x86 hardware do part of the context saving in ISS, by passing the thread context into the TSS before leaving to user-land * use one exception vector for all ARM platforms including Arm_v6 Fix #2091 |
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| 32bit.mk | ||
| 64bit.mk | ||
| arm_v6.mk | ||
| arm_v7.mk | ||
| arm_v7a.mk | ||
| arm.mk | ||
| arndale.mk | ||
| cortex_a8.mk | ||
| cortex_a9.mk | ||
| cortex_a15.mk | ||
| experimental.mk | ||
| exynos5.mk | ||
| fpu_vfpv3.mk | ||
| imx6.mk | ||
| imx53_qsb.mk | ||
| imx53.mk | ||
| odroid_x2.mk | ||
| odroid_xu.mk | ||
| panda.mk | ||
| pbxa9.mk | ||
| release.mk | ||
| riscv.mk | ||
| rpi.mk | ||
| usb_armory.mk | ||
| wand_quad.mk | ||
| x86_32.mk | ||
| x86_64.mk | ||
| x86.mk | ||
| zynq_qemu.mk | ||
| zynq.mk | ||