mirror of
https://github.com/genodelabs/genode.git
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275 lines
7.5 KiB
C++
275 lines
7.5 KiB
C++
/*
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* \brief Driver base for i.MX31 UART-module
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* \author Norman Feske
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* \author Martin Stein
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* \date 2012-08-30
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__UART__IMX31_UART_BASE_H_
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#define _INCLUDE__DRIVERS__UART__IMX31_UART_BASE_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Genode
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{
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/**
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* Driver base for i.MX31 UART-module
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*/
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class Imx31_uart_base : Mmio
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{
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/**
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* Control register 1
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*/
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struct Cr1 : Register<0x80, 32>
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{
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struct Uart_en : Bitfield<0, 1> { }; /* enable UART */
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struct Doze : Bitfield<1, 1> { }; /* disable on doze */
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struct At_dma_en : Bitfield<2, 1> { }; /* aging DMA
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* timer on */
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struct Tx_dma_en : Bitfield<3, 1> { }; /* TX ready DMA on */
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struct Snd_brk : Bitfield<4, 1> { }; /* send breaks */
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struct Rtsd_en : Bitfield<5, 1> { }; /* RTS delta IRQ on */
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struct Tx_mpty_en : Bitfield<6, 1> { }; /* TX empty IRQ on */
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struct Ir_en : Bitfield<7, 1> { }; /* enable infrared */
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struct Rx_dma_en : Bitfield<8, 1> { }; /* RX ready DMA on */
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struct R_rdy_en : Bitfield<9, 1> { }; /* RX ready IRQ on */
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struct Icd : Bitfield<10, 2> /* idle IRQ condition */
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{
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enum { IDLE_4_FRAMES = 0 };
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};
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struct Id_en : Bitfield<12, 1> { }; /* enable idle IRQ */
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struct T_rdy_en : Bitfield<13, 1> { }; /* TX ready IRQ on */
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struct Adbr : Bitfield<14, 1> { }; /* enable baud-rate
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* auto detect */
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struct Ad_en : Bitfield<15, 1> { }; /* enable ADBR IRQ */
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Uart_en::bits(1) |
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Doze::bits(0) |
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At_dma_en::bits(0) |
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Tx_dma_en::bits(0) |
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Snd_brk::bits(0) |
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Rtsd_en::bits(0) |
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Tx_mpty_en::bits(0) |
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Ir_en::bits(0) |
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Rx_dma_en::bits(0) |
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R_rdy_en::bits(0) |
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Id_en::bits(0) |
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T_rdy_en::bits(0) |
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Adbr::bits(0) |
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Ad_en::bits(0);
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}
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};
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/**
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* Control register 2
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*/
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struct Cr2 : Register<0x84, 32>
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{
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struct S_rst : Bitfield<0, 1> /* SW reset bit */
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{
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enum { NO_RESET = 1 };
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};
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struct Rx_en : Bitfield<1, 1> { }; /* enable receiver */
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struct Tx_en : Bitfield<2, 1> { }; /* enable transmitter */
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struct At_en : Bitfield<3, 1> { }; /* enable aging timer */
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struct Rts_en : Bitfield<4, 1> { }; /* send request IRQ on */
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struct Ws : Bitfield<5, 1> /* select word size */
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{
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enum { _8_BITS = 1 };
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};
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struct Stpb : Bitfield<6, 1> /* number of stop bits */
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{
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enum { _1_BIT = 0 };
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};
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struct Pr_en : Bitfield<8, 1> { }; /* enable parity */
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struct Esc_en : Bitfield<11, 1> { }; /* escape detection on */
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struct Ctsc : Bitfield<13, 1> /* select CTS control */
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{
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enum { BY_RECEIVER = 1 };
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};
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struct Irts : Bitfield<14, 1> { }; /* ignore RTS pin */
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struct Esci : Bitfield<15, 1> { }; /* enable escape IRQ */
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return S_rst::bits(S_rst::NO_RESET) |
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Rx_en::bits(0) |
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Tx_en::bits(1) |
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At_en::bits(0) |
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Rts_en::bits(0) |
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Ws::bits(Ws::_8_BITS) |
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Stpb::bits(Stpb::_1_BIT) |
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Pr_en::bits(0) |
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Esc_en::bits(0) |
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Ctsc::bits(Ctsc::BY_RECEIVER) |
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Irts::bits(1) |
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Esci::bits(0);
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}
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};
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/**
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* Control register 3
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*/
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struct Cr3 : Register<0x88, 32>
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{
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struct Rxdmux_sel : Bitfield<2, 1> { }; /* use muxed RXD */
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struct Aci_en : Bitfield<0, 1> { }; /* autobaud count IRQ on */
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struct Dtrd_en : Bitfield<3, 1> { }; /* data terminal ready
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* delta IRQ on */
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struct Awak_en : Bitfield<4, 1> { }; /* wake IRQ on */
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struct Air_int_en : Bitfield<5, 1> { }; /* IR wake IRQ on */
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struct Rx_ds_en : Bitfield<6, 1> { }; /* RX status IRQ on */
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struct Ad_nimp : Bitfield<7, 1> { }; /* autobaud detect off */
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struct Ri_en : Bitfield<8, 1> { }; /* ring indicator IRQ on */
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struct Dcd_en : Bitfield<9, 1> { }; /* data carrier detect
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* IRQ on */
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struct Dsr : Bitfield<10,1> { }; /* DSR/DTR output */
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struct Frame_en : Bitfield<11,1> { }; /* frame error IRQ on */
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struct Parity_en : Bitfield<12,1> { }; /* parity error IRQ on */
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struct Dtr_en : Bitfield<13,1> { }; /* data terminal ready
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* IRQ on */
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struct Dpec_ctrl : Bitfield<14,2> { }; /* DTR/DSR IRQ edge
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* control */
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Aci_en::bits(0) |
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Rxdmux_sel::bits(0) |
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Dtrd_en::bits(0) |
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Awak_en::bits(0) |
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Air_int_en::bits(0) |
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Rx_ds_en::bits(0) |
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Ad_nimp::bits(1) |
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Ri_en::bits(0) |
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Dcd_en::bits(0) |
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Dsr::bits(0) |
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Frame_en::bits(0) |
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Parity_en::bits(0) |
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Dtr_en::bits(0) |
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Dpec_ctrl::bits(0);
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}
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};
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/**
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* Control register 4
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*/
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struct Cr4 : Register<0x8c, 32>
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{
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struct Dr_en : Bitfield<0, 1> { }; /* RX data ready IRQ on */
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struct Or_en : Bitfield<1, 1> { }; /* RX overrun IRQ on */
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struct Bk_en : Bitfield<2, 1> { }; /* BREAK IRQ on */
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struct Tc_en : Bitfield<3, 1> { }; /* TX complete IRQ on */
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struct Lp_dis : Bitfield<4, 1> { }; /* low power off */
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struct IR_sc : Bitfield<5, 1> { }; /* use UART ref clock
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* for vote logic */
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struct Id_dma_en : Bitfield<6, 1> { }; /* idle DMA IRQ on */
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struct Wake_en : Bitfield<7, 1> { }; /* WAKE IRQ on */
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struct IR_en : Bitfield<8, 1> { }; /* serial IR IRQ on */
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struct Cts_level : Bitfield<10,6> { }; /* CTS trigger level*/
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Dr_en::bits(0) |
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Or_en::bits(0) |
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Bk_en::bits(0) |
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Tc_en::bits(0) |
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Lp_dis::bits(0) |
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IR_sc::bits(0) |
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Id_dma_en::bits(0) |
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Wake_en::bits(0) |
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IR_en::bits(0) |
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Cts_level::bits(0);
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}
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};
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/**
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* Status register 2
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*/
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struct Sr2 : Register<0x98, 32>
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{
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struct Txdc : Bitfield<3, 1> { }; /* transmission complete */
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};
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/**
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* Transmitter register
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*/
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struct Txd : Register<0x40, 32>
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{
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struct Tx_data : Bitfield<0, 8> { }; /* transmit data */
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};
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/**
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* Transmit character 'c' without care about its type
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*/
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inline void _put_char(char const c)
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{
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while (!read<Sr2::Txdc>()) ;
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write<Txd::Tx_data>(c);
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}
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public:
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/**
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* Constructor
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*
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* \param base device MMIO base
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*/
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explicit Imx31_uart_base(addr_t const base) : Mmio(base)
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{
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write<Cr1>(Cr1::init_value());
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write<Cr2>(Cr2::init_value());
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write<Cr3>(Cr3::init_value());
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write<Cr4>(Cr4::init_value());
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}
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/**
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* Print character 'c' through the UART
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*/
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inline void put_char(char const c)
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{
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enum { ASCII_LINE_FEED = 10,
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ASCII_CARRIAGE_RETURN = 13 };
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/* prepend line feed with carriage return */
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if (c == ASCII_LINE_FEED) _put_char(ASCII_CARRIAGE_RETURN);
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/* transmit character */
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_put_char(c);
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}
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};
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}
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#endif /* _INCLUDE__DRIVERS__UART__IMX31_UART_BASE_H_ */
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