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31d57a6257
Implies support for the ARMv6 architecture through 'base-hw'. Get rid of 'base/include/drivers' expect of 'base/include/drivers/uart'. Merge with the support for trustzone on VEA9X4 that came from Stefan Kalkowski. Leave board drivers in 'base/include/platform'. Rework structure of the other drivers that were moved to 'base_hw/src/core' and those that came with the trustzone support. Beautify further stuff in 'base_hw'. Test 'nested_init' with 'hw_imx31' (hardware) and 'hw_panda_a2' (hardware), 'demo' and 'signal' with 'hw_pbxa9' (qemu) and 'hw_vea9x4' (hardware, no trustzone), and 'vmm' with 'hw_vea9x4' (hardware, with trustzone).
84 lines
1.9 KiB
C++
84 lines
1.9 KiB
C++
/*
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* \brief CPU state
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* \author Norman Feske
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* \author Stefan Kalkowski
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* \author Martin Stein
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* \date 2011-05-06
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ARM__CPU__CPU_STATE_H_
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#define _INCLUDE__ARM__CPU__CPU_STATE_H_
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/* Genode includes */
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#include <base/stdint.h>
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namespace Genode {
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/**
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* Basic CPU state
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*/
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struct Cpu_state
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{
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/**
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* Native exception types
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*/
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enum Cpu_exception {
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RESET = 1,
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UNDEFINED_INSTRUCTION = 2,
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SUPERVISOR_CALL = 3,
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PREFETCH_ABORT = 4,
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DATA_ABORT = 5,
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INTERRUPT_REQUEST = 6,
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FAST_INTERRUPT_REQUEST = 7,
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};
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/**
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* Registers
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*/
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addr_t r0, r1, r2, r3, r4, r5, r6,
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r7, r8, r9, r10, r11, r12; /* general purpose register 0..12 */
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addr_t sp; /* stack pointer */
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addr_t lr; /* link register */
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addr_t ip; /* instruction pointer */
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addr_t cpsr; /* current program status register */
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addr_t cpu_exception; /* last hardware exception */
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};
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/**
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* Extend CPU state by banked registers
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*/
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struct Cpu_state_modes : Cpu_state
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{
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/**
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* Common banked registers for exception modes
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*/
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struct Mode_state {
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enum Mode {
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UND, /* Undefined */
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SVC, /* Supervisor */
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ABORT, /* Abort */
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IRQ, /* Interrupt */
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FIQ, /* Fast Interrupt */
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MAX
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};
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addr_t spsr; /* saved program status register */
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addr_t sp; /* banked stack pointer */
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addr_t lr; /* banked link register */
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};
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Mode_state mode[Mode_state::MAX]; /* exception mode registers */
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addr_t fiq_r[5]; /* fast-interrupt mode r8-r12 */
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};
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}
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#endif /* _INCLUDE__ARM__CPU__CPU_STATE_H_ */
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