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400 lines
10 KiB
C++
400 lines
10 KiB
C++
/*
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* \brief Driver for the Xilinx LogiCORE XPS Timer/Counter IP 1.02
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* \author Martin stein
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* \date 2010-06-22
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*/
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/*
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* Copyright (C) 2010-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DEVICES__XILINX_XPS_TIMER_H_
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#define _INCLUDE__DEVICES__XILINX_XPS_TIMER_H_
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#include <cpu/config.h>
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namespace Xilinx {
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/**
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* Driver for the Xilinx LogiCORE XPS Timer/Counter IP 1.02
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*/
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class Xps_timer
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{
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public:
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/**
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* CPU dependencies
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*/
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typedef Cpu::word_t word_t;
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typedef Cpu::addr_t addr_t;
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typedef Cpu::size_t size_t;
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typedef Cpu::uint32_t uint32_t;
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/**
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* MMIO register
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*/
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typedef uint32_t Register;
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/**
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* Constructor, resets timer, overwrites timer value with '0'
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*/
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inline Xps_timer(addr_t const &base);
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/**
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* Destructor, resets timer, overwrites timer value with '0'
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*/
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inline ~Xps_timer();
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/**
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* Overwrite timer value with X>0, count downwards to '0', set the
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* IRQ output to '1' for one cycle and simultaneously start counting
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* downwards again from X, and so on ...
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*
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* \param value the value X
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*/
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inline void run_periodic(unsigned int const &value);
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/**
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* Overwrite timer value with X>0, count downwards to '0', set the
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* IRQ output to '1' for one cycle and simultaneously start counting
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* downwards from max_value() to '0', and so on ...
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*
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* \param value the value X
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*/
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inline void run_circulating(unsigned int const &value);
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/**
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* Overwrite timer value with X>0, count downwards to '0', set the
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* IRQ output to '1' for one cycle, timer value remains '0'
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*
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* \param value the value X
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*/
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inline void run_oneshot(unsigned int const &value);
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/**
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* Prepare a 'run_oneshot()'-like run that shall be triggered with
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* simple means. Useful for starting the timer out of assembly-code.
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*
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* \param value native time-value used to assess the delay
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* of the timer IRQ as of the triggering
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* \param start_val at this address the start value gets deposited
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* \param start_reg at this address an address X gets deposited
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* writing the start value to X later starts the
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* timer as prepared
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*/
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inline void prepare_oneshot(unsigned int const & value,
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volatile Register * & start_reg,
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Register & start_val);
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/**
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* Current timer value
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*/
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inline unsigned int value();
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/**
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* Return the timers current value and determine if the timer has hit '0'
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* before the returned value and after the last time we started it or called
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* 'period_value' on it. Called during non-periodic runs 'rolled_over'
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* becomes 'true' if value is '0' and 'false' otherwise
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*
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* Enable exclusive access only to this function to ensure correct behavior!
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* This function delays the timer about the duration of a few cpu cycles!
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*/
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inline unsigned int period_value(bool * const & rolled_over);
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/**
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* Size of the MMIO provided by the timer device
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*/
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static inline size_t size();
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/**
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* Maximum timer value
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*/
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static inline unsigned int max_value();
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/**
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* Converting a native time value to milliseconds
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*/
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static inline unsigned int native_to_msec(unsigned int const &v);
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/**
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* Converting milliseconds to a native time value
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*/
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static inline unsigned int msec_to_native(unsigned int const &v);
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/**
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* Converting a native time value to microseconds
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*/
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static inline unsigned int native_to_usec(unsigned int const &v);
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/**
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* Converting microseconds to a native time value
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*/
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static inline unsigned int usec_to_native(unsigned int const &v);
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private:
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/**
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* General constraints
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*/
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enum {
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WORD_SIZE = sizeof(word_t),
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BYTE_WIDTH = Cpu::BYTE_WIDTH,
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FREQUENCY_PER_US = 62,
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};
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/**
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* Registers
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*/
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enum {
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/* Control/status register */
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RTCSR0_OFFSET = 0*WORD_SIZE,
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/* Load register, written to RTCR when RTCSR[LOAD]='1' */
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RTLR0_OFFSET = 1*WORD_SIZE,
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/* On timer/counter register the counting is done */
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RTCR0_OFFSET = 2*WORD_SIZE,
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/* Respectively for the second timer/counter module */
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RTCSR1_OFFSET = 4*WORD_SIZE,
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RTLR1_OFFSET = 5*WORD_SIZE,
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RTCR1_OFFSET = 6*WORD_SIZE,
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MMIO_SIZE = 8*WORD_SIZE,
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/* r/w '0': generate timer mode
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* r/w '1': capture timer mode */
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RTCSR_MDT_LSHIFT = 0,
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/* r/w '0': count upward mode
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* r/w '1': count downward mode */
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RTCSR_UDT_LSHIFT = 1,
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/* r/w '0': external generate signal disabled mode
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* r/w '1': external generate signal enabled mode */
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RTCSR_GENT_LSHIFT = 2,
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/* r/w '0': external capture trigger disabled mode
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* r/w '1': external capture trigger enabled mode */
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RTCSR_CAPT_LSHIFT = 3,
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/* r/w '0': hold values mode
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* r/w '0': auto reload (generate timer) / overwrite (capture timer) mode */
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RTCSR_ARHT_LSHIFT = 4,
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/* w/r '0': disable loading mode
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* w/r '1': loading timer mode (RTCR=RTLR) */
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RTCSR_LOAD_LSHIFT = 5,
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/* w/r '0': throw no IRQ mode (doesn't affect RTCSR[TINT])
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* w/r '1': throw IRQ on 0-1-edge at RTCSR[TINT] mode */
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RTCSR_ENIT_LSHIFT = 6,
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/* w/r '0': don't count (RTCR remains constant)
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* w/r '1': count on RTCR */
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RTCSR_ENT_LSHIFT = 7,
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/* r '0': no IRQ has occured
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* r '1': IRQ has occured
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* w '0': no effect
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* w '1': RTCSR[TINT]=0 */
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RTCSR_TINT_LSHIFT = 8,
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/* r/w '0': pulse width modulation disabled mode
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* r/w '1': pulse width modulation enabled mode */
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RTCSR_PWM_LSHIFT = 9,
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/* w/r '0': nothing
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* w/r '1': RTCSR[ENT]='1' for all timer/counter modules */
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RTCSR_ENALL_LSHIFT = 10,
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};
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/**
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* Controls for RTCSR
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*/
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enum {
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RUN_ONCE = 0
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| 0 << RTCSR_MDT_LSHIFT
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| 1 << RTCSR_UDT_LSHIFT
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| 0 << RTCSR_CAPT_LSHIFT
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| 0 << RTCSR_GENT_LSHIFT
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| 0 << RTCSR_ARHT_LSHIFT
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| 0 << RTCSR_LOAD_LSHIFT
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| 1 << RTCSR_ENIT_LSHIFT
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| 1 << RTCSR_ENT_LSHIFT
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| 1 << RTCSR_TINT_LSHIFT
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| 0 << RTCSR_PWM_LSHIFT
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| 0 << RTCSR_ENALL_LSHIFT
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,
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STOP_N_LOAD = 0
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| 0 << RTCSR_MDT_LSHIFT
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| 1 << RTCSR_UDT_LSHIFT
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| 0 << RTCSR_CAPT_LSHIFT
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| 0 << RTCSR_GENT_LSHIFT
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| 0 << RTCSR_ARHT_LSHIFT
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| 1 << RTCSR_LOAD_LSHIFT
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| 0 << RTCSR_ENIT_LSHIFT
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| 0 << RTCSR_ENT_LSHIFT
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| 0 << RTCSR_TINT_LSHIFT
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| 0 << RTCSR_PWM_LSHIFT
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| 0 << RTCSR_ENALL_LSHIFT
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,
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RUN_PERIODIC = RUN_ONCE
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| 1 << RTCSR_ARHT_LSHIFT
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,
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STOP_N_RESET = STOP_N_LOAD
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| 1 << RTCSR_TINT_LSHIFT
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,
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};
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/**
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* Absolute register addresses
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*/
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volatile Register *const _rtcsr0;
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volatile Register *const _rtlr0;
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volatile Register *const _rtcr0;
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volatile Register *const _rtcsr1;
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volatile Register *const _rtlr1;
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volatile Register *const _rtcr1;
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};
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}
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Xilinx::Xps_timer::Xps_timer(addr_t const &base)
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:
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_rtcsr0((Register *)(base + RTCSR0_OFFSET)),
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_rtlr0((Register *)(base + RTLR0_OFFSET)),
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_rtcr0((Register *)(base + RTCR0_OFFSET)),
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_rtcsr1((Register *)(base + RTCSR1_OFFSET)),
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_rtlr1((Register *)(base + RTLR1_OFFSET)),
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_rtcr1((Register *)(base + RTCR1_OFFSET))
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{
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*_rtcsr0 = STOP_N_RESET;
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*_rtcsr1 = STOP_N_RESET;
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*_rtlr0 = 0;
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}
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Xilinx::Xps_timer::size_t Xilinx::Xps_timer::size()
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{
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return (size_t)MMIO_SIZE;
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}
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unsigned int Xilinx::Xps_timer::max_value() { return ((unsigned int)~0); }
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void Xilinx::Xps_timer::prepare_oneshot(unsigned int const & value,
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volatile Register * & start_reg,
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Register & start_val)
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{
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*_rtcsr0 = STOP_N_LOAD;
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*_rtlr0 = value;
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start_reg = _rtcsr0;
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start_val = RUN_ONCE;
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}
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void Xilinx::Xps_timer::run_circulating(unsigned int const &value)
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{
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*_rtcsr0 = STOP_N_LOAD;
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*_rtlr0 = value;
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*_rtcsr0 = RUN_PERIODIC;
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*_rtlr0 = max_value();
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}
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void Xilinx::Xps_timer::run_periodic(unsigned int const &value)
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{
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*_rtcsr0 = STOP_N_LOAD;
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*_rtlr0 = value;
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*_rtcsr0 = RUN_PERIODIC;
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}
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void Xilinx::Xps_timer::run_oneshot(unsigned int const &value)
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{
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*_rtcsr0 = STOP_N_LOAD;
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*_rtlr0 = value;
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*_rtcsr0 = RUN_ONCE;
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}
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unsigned int Xilinx::Xps_timer::value() { return *_rtcr0; }
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unsigned int Xilinx::Xps_timer::period_value(bool * const &rolled_over)
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{
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if(!(*_rtcsr0 & (1 << RTCSR_ARHT_LSHIFT))){
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/* this is no periodic run */
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unsigned int const v = *_rtcr0;
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*rolled_over = !(v);
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return value();
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}
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/* 2 measurements are necessary to ensure that
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* 'rolled_over' and the returned value are fit together
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* because we can not halt the timer or read both simulanously */
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unsigned int const v1 = *_rtcr0;
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*rolled_over = (bool)(*_rtcsr0 & (1 << RTCSR_TINT_LSHIFT));
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unsigned int const v2 = *_rtcr0;
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if(*rolled_over) {
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/* v2 must be a value the timer had after rolling over, so restart
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* the timer with the current value but RTCSR[TINT] reset */
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unsigned int const initial_rtlr = *_rtlr0;
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unsigned int const restart_n_reset = *_rtcsr0 | (1 << RTCSR_TINT_LSHIFT);
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*_rtlr0 = *_rtcr0; // timer gets delayed about the
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*_rtcsr0 = restart_n_reset; // duration of these two operations
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*_rtlr0 = initial_rtlr;
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return v2;
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}
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/* v1 must be a value that the timer had before rolling
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* over, so we don't have to reset the "rolled over" status even
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* if the timer has rolled over till now */
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return v1;
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}
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Xilinx::Xps_timer::~Xps_timer()
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{
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*_rtcsr0 = STOP_N_RESET;
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*_rtcsr1 = STOP_N_RESET;
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}
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unsigned int Xilinx::Xps_timer::native_to_msec(unsigned int const &v)
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{
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return 1000*native_to_usec(v);
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}
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unsigned int Xilinx::Xps_timer::msec_to_native(unsigned int const &v)
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{
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return 1000*usec_to_native(v);
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}
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unsigned int Xilinx::Xps_timer::native_to_usec(unsigned int const &v)
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{
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return v/FREQUENCY_PER_US;
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}
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unsigned int Xilinx::Xps_timer::usec_to_native(unsigned int const &v)
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{
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return v*FREQUENCY_PER_US;
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}
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#endif /* _INCLUDE__DEVICES__XILINX_XPS_TIMER_H_ */
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