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7aff1895bf
This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
96 lines
2.0 KiB
C++
96 lines
2.0 KiB
C++
/**
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* \brief Driver for the Realview PBXA9 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__SPEC__PBXA9__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__SPEC__PBXA9__DRIVERS__BOARD_BASE_H_
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namespace Genode { struct Board_base; }
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/**
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* Driver for the Realview PBXA9 board
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*/
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struct Genode::Board_base
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{
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enum {
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/* normal RAM */
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RAM_0_BASE = 0x70000000,
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RAM_0_SIZE = 0x20000000,
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RAM_1_BASE = 0x20000000,
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RAM_1_SIZE = 0x10000000,
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/* device IO memory */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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MMIO_1_BASE = 0x4e000000,
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MMIO_1_SIZE = 0x01000000,
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NORTHBRIDGE_AHB_BASE = 0x10020000,
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NORTHBRIDGE_AHB_SIZE = 768*1024,
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/* southbridge */
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SOUTHBRIDGE_APB_BASE = 0x10000000,
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SOUTHBRIDGE_APB_SIZE = 128*1024,
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/* clocks */
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OSC_6_CLOCK = 24*1000*1000,
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/* system controller */
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SYSTEM_CONTROL_MMIO_BASE = 0x10000000,
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/* CPU */
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CORTEX_A9_PRIVATE_TIMER_CLK = 100000000,
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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/* L2 cache controller */
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PL310_MMIO_BASE = 0x1f002000,
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PL310_MMIO_SIZE = 0x00001000,
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/* UART */
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PL011_0_MMIO_BASE = 0x10009000,
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PL011_0_MMIO_SIZE = 0x00001000,
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PL011_0_CLOCK = OSC_6_CLOCK,
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PL011_0_IRQ = 44,
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PL011_1_IRQ = 45,
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PL011_2_IRQ = 46,
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PL011_3_IRQ = 47,
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/* timer */
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SP804_0_1_MMIO_BASE = 0x10011000,
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SP804_0_1_MMIO_SIZE = 0x00001000,
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SP804_0_1_IRQ = 36,
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SP804_0_1_CLOCK = 1000*1000,
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/* keyboard & mouse */
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KMI_0_IRQ = 52,
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KMI_1_IRQ = 53,
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/* LAN */
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ETHERNET_IRQ = 60,
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/* SD card */
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PL180_IRQ_0 = 49,
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PL180_IRQ_1 = 50,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
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/* wether board provides security extension */
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SECURITY_EXTENSION = 0,
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};
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};
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#endif /* _INCLUDE__SPEC__PBXA9__DRIVERS__BOARD_BASE_H_ */
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