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4e97a6511b
* Instead of always re-load page-tables when a thread context is switched only do this when another user PD's thread is the next target, core-threads are always executed within the last PD's page-table set * remove the concept of the mode transition * instead map the exception vector once in bootstrap code into kernel's memory segment * when a new page directory is constructed for a user PD, copy over the top-level kernel segment entries on RISCV and X86, on ARM we use a designated page directory register for the kernel segment * transfer the current CPU id from bootstrap to core/kernel in a register to ease first stack address calculation * align cpu context member of threads and vms, because of x86 constraints regarding the stack-pointer loading * introduce Align_at template for members with alignment constraints * let the x86 hardware do part of the context saving in ISS, by passing the thread context into the TSS before leaving to user-land * use one exception vector for all ARM platforms including Arm_v6 Fix #2091
11 lines
339 B
Makefile
11 lines
339 B
Makefile
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
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SRC_CC += bootstrap/spec/x86_64/platform_muen.cc
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SRC_CC += lib/muen/sinfo.cc
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SRC_CC += hw/spec/64bit/memory_map.cc
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SRC_S += bootstrap/spec/x86_64/crt0.s
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SRC_S += bootstrap/spec/x86_64/crt0_translation_table_muen.s
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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