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1668983efa
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880
50 lines
1.2 KiB
C++
50 lines
1.2 KiB
C++
/*
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* \brief CPU state
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* \author Sebastian Sumpf
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* \date 2015-06-01
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*/
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/*
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* Copyright (C) 2015-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__RISCV__CPU__CPU_STATE_H_
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#define _INCLUDE__RISCV__CPU__CPU_STATE_H_
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/* Genode includes */
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#include <base/stdint.h>
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namespace Genode { struct Cpu_state; }
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struct Genode::Cpu_state
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{
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enum Cpu_exception {
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INSTRUCTION_UNALIGNED = 0,
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INSTRUCTION_PAGE_FAULT = 1,
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INSTRUCTION_ILLEGAL = 2,
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BREAKPOINT = 3,
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LOAD_UNALIGNED = 4,
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LOAD_PAGE_FAULT = 5,
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STORE_UNALIGNED = 6,
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STORE_PAGE_FAULT = 7,
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ECALL_FROM_USER = 8,
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ECALL_FROM_SUPERVISOR = 9,
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ECALL_FROM_HYPERVISOR = 10,
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ECALL_FROM_MACHINE = 11,
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RESET = 16,
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IRQ_FLAG = 1UL << 63,
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};
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addr_t ip, cpu_exception, ra, sp, gp, tp, t0, t1, t2, s0, s1, a0, a1, a2,
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a3, a4, a5, a6, a7, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3,
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t4, t5, t6;
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bool is_irq() { return cpu_exception & IRQ_FLAG; }
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unsigned irq() { return cpu_exception ^ IRQ_FLAG; }
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};
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#endif /* _INCLUDE__RISCV__CPU__CPU_STATE_H_ */
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