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1208d14681
* Adds public timeout syscalls to kernel API
* Kernel::timeout installs a timeout and binds a signal context to it that
shall trigger once the timeout expired
* With Kernel::timeout_max_us, one can get the maximum installable timeout
* Kernel::timeout_age_us returns the time that has passed since the
calling threads last timeout installation
* Removes all device specific back-ends for the base-hw timer driver and
implements a generic back-end taht uses the kernel timeout API
* Adds assertions about the kernel timer frequency that originate from the
requirements of the the kernel timeout API and adjusts all timers
accordingly by using the their internal dividers
* Introduces the Kernel::Clock class. As member of each Kernel::Cpu object
it combines the management of the timer of the CPU with a timeout scheduler.
Not only the timeout API uses the timeout scheduler but also the CPUs job
scheduler for installing scheduling timeouts.
* Introduces the Kernel::time_t type for timer tic values and values inherited
from timer tics (like microseconds).
Fixes #1972
110 lines
2.6 KiB
C++
110 lines
2.6 KiB
C++
/*
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* \brief Driver for the OMAP4 PandaBoard revision A2
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__SPEC__PANDA__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__SPEC__PANDA__DRIVERS__BOARD_BASE_H_
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namespace Genode { struct Board_base; }
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/**
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* Driver for the OMAP4 PandaBoard revision A2
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*/
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struct Genode::Board_base
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{
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enum {
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/* device IO memory */
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MMIO_0_BASE = 0x48000000,
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MMIO_0_SIZE = 0x01000000,
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MMIO_1_BASE = 0x4a000000,
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MMIO_1_SIZE = 0x01000000,
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/* normal RAM */
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RAM_0_BASE = 0x80000000,
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RAM_0_SIZE = 0x40000000,
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/* clocks */
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SYS_CLK = 38400000,
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/* UART controllers */
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TL16C750_1_MMIO_BASE = MMIO_0_BASE + 0x6a000,
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TL16C750_2_MMIO_BASE = MMIO_0_BASE + 0x6c000,
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TL16C750_3_MMIO_BASE = MMIO_0_BASE + 0x20000,
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TL16C750_4_MMIO_BASE = MMIO_0_BASE + 0x6e000,
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TL16C750_MMIO_SIZE = 0x2000,
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TL16C750_CLOCK = 48*1000*1000,
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TL16C750_1_IRQ = 104,
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TL16C750_2_IRQ = 105,
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TL16C750_3_IRQ = 106,
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TL16C750_4_IRQ = 102,
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/* USB */
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HSUSB_EHCI_IRQ = 109,
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/* timer modules */
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GP_TIMER_3_IRQ = 71,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x48240000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 350000000,
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CORTEX_A9_PRIVATE_TIMER_DIV = 175,
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CORTEX_A9_WUGEN_MMIO_BASE = 0x48281000,
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CORTEX_A9_SCU_MMIO_BASE = 0x48240000,
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/* L2 cache */
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PL310_MMIO_BASE = 0x48242000,
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PL310_MMIO_SIZE = 0x00001000,
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/* display subsystem */
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DSS_MMIO_BASE = 0x58000000,
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DSS_MMIO_SIZE = 0x00001000,
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DISPC_MMIO_BASE = 0x58001000,
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DISPC_MMIO_SIZE = 0x00001000,
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HDMI_MMIO_BASE = 0x58006000,
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HDMI_MMIO_SIZE = 0x00001000,
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/* GPIO */
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GPIO1_MMIO_BASE = 0x4a310000,
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GPIO1_MMIO_SIZE = 0x1000,
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GPIO1_IRQ = 29 + 32,
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GPIO2_MMIO_BASE = 0x48055000,
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GPIO2_MMIO_SIZE = 0x1000,
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GPIO2_IRQ = 30 + 32,
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GPIO3_MMIO_BASE = 0x48057000,
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GPIO3_MMIO_SIZE = 0x1000,
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GPIO3_IRQ = 31 + 32,
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GPIO4_MMIO_BASE = 0x48059000,
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GPIO4_MMIO_SIZE = 0x1000,
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GPIO4_IRQ = 32 + 32,
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GPIO5_MMIO_BASE = 0x4805b000,
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GPIO5_MMIO_SIZE = 0x1000,
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GPIO5_IRQ = 33 + 32,
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GPIO6_MMIO_BASE = 0x4805d000,
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GPIO6_MMIO_SIZE = 0x1000,
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GPIO6_IRQ = 34 + 32,
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/* SD card */
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HSMMC_IRQ = 115,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
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/* wether board provides security extension */
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SECURITY_EXTENSION = 0,
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};
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};
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#endif /* _INCLUDE__SPEC__PANDA__DRIVERS__BOARD_BASE_H_ */
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