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115 lines
2.4 KiB
C++
115 lines
2.4 KiB
C++
/*
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* \brief Console backend for NOVA
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* \author Norman Feske
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* \author Alexander Boettcher
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* \date 2009-12-28
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*/
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/*
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* Copyright (C) 2009-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__SPEC__X86__DRIVERS__UART_BASE_H_
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#define _INCLUDE__SPEC__X86__DRIVERS__UART_BASE_H_
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/* Genode includes */
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#include <base/stdint.h>
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namespace Genode { class X86_uart_base; }
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class Genode::X86_uart_base
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{
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private:
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uint16_t _port;
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enum {
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COMPORT_DATA_OFFSET = 0,
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COMPORT_STATUS_OFFSET = 5,
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STATUS_THR_EMPTY = 0x20, /* transmitter hold register empty */
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STATUS_DHR_EMPTY = 0x40, /* data hold register empty - data completely sent */
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};
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/**
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* Read byte from I/O port
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*/
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uint8_t _inb(uint16_t port)
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{
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uint8_t res;
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asm volatile ("inb %%dx, %0" :"=a"(res) :"Nd"(port));
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return res;
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}
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/**
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* Write byte to I/O port
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*/
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void _outb(uint16_t port, uint8_t val)
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{
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asm volatile ("outb %b0, %w1" : : "a" (val), "Nd" (port));
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}
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public:
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X86_uart_base(addr_t const port, unsigned const clock,
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unsigned const baud_rate)
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: _port(port)
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{
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/**
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* Initialize serial port
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*
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* Based on 'init_serial' of L4ka::Pistachio's 'kdb/platform/pc99/io.cc'
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*/
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if (!port)
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return;
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const unsigned
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IER = port + 1,
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EIR = port + 2,
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LCR = port + 3,
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MCR = port + 4,
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LSR = port + 5,
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MSR = port + 6,
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DLLO = port + 0,
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DLHI = port + 1;
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_outb(LCR, 0x80); /* select bank 1 */
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for (volatile int i = 10000000; i--; );
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_outb(DLLO, (115200/baud_rate) >> 0);
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_outb(DLHI, (115200/baud_rate) >> 8);
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_outb(LCR, 0x03); /* set 8,N,1 */
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_outb(IER, 0x00); /* disable interrupts */
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_outb(EIR, 0x07); /* enable FIFOs */
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_outb(MCR, 0x0b); /* force data terminal ready */
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_outb(IER, 0x01); /* enable RX interrupts */
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_inb(IER);
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_inb(EIR);
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_inb(LCR);
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_inb(MCR);
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_inb(LSR);
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_inb(MSR);
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}
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void put_char(char const c)
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{
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if (!_port)
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return;
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/* wait until serial port is ready */
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Genode::uint8_t ready = STATUS_THR_EMPTY;
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while ((_inb(_port + COMPORT_STATUS_OFFSET) & ready) != ready);
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/* output character */
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_outb(_port + COMPORT_DATA_OFFSET, c);
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}
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};
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#endif /* _INCLUDE__SPEC__X86__DRIVERS__UART_BASE_H_ */
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