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1208d14681
* Adds public timeout syscalls to kernel API
* Kernel::timeout installs a timeout and binds a signal context to it that
shall trigger once the timeout expired
* With Kernel::timeout_max_us, one can get the maximum installable timeout
* Kernel::timeout_age_us returns the time that has passed since the
calling threads last timeout installation
* Removes all device specific back-ends for the base-hw timer driver and
implements a generic back-end taht uses the kernel timeout API
* Adds assertions about the kernel timer frequency that originate from the
requirements of the the kernel timeout API and adjusts all timers
accordingly by using the their internal dividers
* Introduces the Kernel::Clock class. As member of each Kernel::Cpu object
it combines the management of the timer of the CPU with a timeout scheduler.
Not only the timeout API uses the timeout scheduler but also the CPUs job
scheduler for installing scheduling timeouts.
* Introduces the Kernel::time_t type for timer tic values and values inherited
from timer tics (like microseconds).
Fixes #1972
73 lines
1.6 KiB
C++
73 lines
1.6 KiB
C++
/*
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* \brief Board definitions for the Freescale i.MX6
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Josef Soentgen
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* \author Martin Stein
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* \date 2014-02-25
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*/
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/*
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* Copyright (C) 2014-2016 Ksys Labs LLC
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* Copyright (C) 2014-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__SPEC__IMX6__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__SPEC__IMX6__DRIVERS__BOARD_BASE_H_
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namespace Genode
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{
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/**
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* i.MX6 motherboard
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*/
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struct Board_base;
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}
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struct Genode::Board_base
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{
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enum {
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/* normal RAM */
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RAM0_BASE = 0x10000000,
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RAM0_SIZE = 0x80000000,
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/* device IO memory */
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MMIO_BASE = 0x00000000,
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MMIO_SIZE = 0x10000000,
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UART_1_IRQ = 58,
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UART_1_MMIO_BASE = 0x02020000,
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UART_1_MMIO_SIZE = 0x00004000,
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/* timer */
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EPIT_2_IRQ = 89,
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EPIT_2_MMIO_BASE = 0x020d4000,
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EPIT_2_MMIO_SIZE = 0x00004000,
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/* ARM IP Bus control */
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AIPS_1_MMIO_BASE = 0x0207c000,
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AIPS_1_MMIO_SIZE = 0x00004000,
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AIPS_2_MMIO_BASE = 0x0217c000,
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AIPS_2_MMIO_SIZE = 0x00004000,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 395037500,
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CORTEX_A9_PRIVATE_TIMER_DIV = 170,
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/* L2 cache controller */
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PL310_MMIO_BASE = 0x00a02000,
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PL310_MMIO_SIZE = 0x00001000,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 5,
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/* wether board provides ARM security extension */
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SECURITY_EXTENSION = 1,
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};
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};
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#endif /* _INCLUDE__SPEC__IMX6__DRIVERS__BOARD_BASE_H_ */
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