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706 lines
17 KiB
C++
706 lines
17 KiB
C++
/*
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* \brief PCI, PCI-x, PCI-Express configuration declarations
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* \author Stefan Kalkowski
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* \date 2021-12-01
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*/
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/*
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* Copyright (C) 2021 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef __INCLUDE__PCI__CONFIG_H__
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#define __INCLUDE__PCI__CONFIG_H__
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#include <base/log.h>
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#include <pci/types.h>
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#include <util/reconstructible.h>
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#include <util/mmio.h>
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namespace Pci {
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struct Config;
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struct Config_type0;
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struct Config_type1;
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enum {
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DEVICES_PER_BUS_MAX = 32,
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FUNCTION_PER_DEVICE_MAX = 8,
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FUNCTION_PER_BUS_MAX = DEVICES_PER_BUS_MAX *
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FUNCTION_PER_DEVICE_MAX,
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FUNCTION_CONFIG_SPACE_SIZE = 4096,
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};
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};
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struct Pci::Config : Genode::Mmio
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{
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struct Vendor : Register<0x0, 16>
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{
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enum { INVALID = 0xffff };
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};
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struct Device : Register<0x2, 16> {};
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struct Command : Register<0x4, 16>
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{
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struct Io_space_enable : Bitfield<0, 1> {};
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struct Memory_space_enable : Bitfield<1, 1> {};
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struct Bus_master_enable : Bitfield<2, 1> {};
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struct Special_cycle_enable : Bitfield<3, 1> {};
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struct Memory_write_invalidate : Bitfield<4, 1> {};
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struct Vga_palette_snoop : Bitfield<5, 1> {};
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struct Parity_error_response : Bitfield<6, 1> {};
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struct Idsel : Bitfield<7, 1> {};
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struct Serror_enable : Bitfield<8, 1> {};
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struct Fast_back_to_back_enable : Bitfield<9, 1> {};
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struct Interrupt_enable : Bitfield<10, 1> {};
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};
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struct Status : Register<0x6, 16>
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{
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struct Interrupt : Bitfield<3,1> {};
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struct Capabilities : Bitfield<4,1> {};
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};
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struct Class_code_rev_id : Register<0x8, 32>
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{
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struct Revision : Bitfield<0, 8> {};
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struct Class_code : Bitfield<8, 24> {};
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};
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struct Iface_class_code : Register<0x9, 8> {};
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struct Sub_class_code : Register<0xa, 8> {};
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struct Base_class_code : Register<0xb, 8>
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{
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enum { BRIDGE = 6 };
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};
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struct Header_type : Register<0xe, 8>
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{
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struct Type : Bitfield<0,7> {};
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struct Multi_function : Bitfield<7,1> {};
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};
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struct Base_address : Mmio
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{
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struct Bar_32bit : Register<0, 32>
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{
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struct Memory_space_indicator : Bitfield<0,1>
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{
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enum { MEMORY = 0, IO = 1 };
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};
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struct Memory_type : Bitfield<1,2>
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{
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enum { SIZE_32BIT = 0, SIZE_64BIT = 2 };
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};
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struct Memory_prefetchable : Bitfield<3,1> {};
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struct Io_base : Bitfield<2, 30> {};
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struct Memory_base : Bitfield<7, 25> {};
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};
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struct Upper_bits : Register<0x4, 32> { };
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Bar_32bit::access_t _conf_value { 0 };
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template <typename REG>
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typename REG::access_t _get_and_set(typename REG::access_t value)
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{
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write<REG>(0xffffffff);
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typename REG::access_t ret = read<REG>();
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write<REG>(value);
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return ret;
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}
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Bar_32bit::access_t _conf()
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{
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/*
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* Initialize _conf_value on demand only to prevent read-write
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* operations on BARs of invalid devices at construction time.
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*/
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if (!_conf_value)
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_conf_value = _get_and_set<Bar_32bit>(read<Bar_32bit>());
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return _conf_value;
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}
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Base_address(Genode::addr_t base) : Mmio(base) { }
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bool valid() { return _conf() != 0; }
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bool memory() {
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return !Bar_32bit::Memory_space_indicator::get(_conf()); }
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bool bit64()
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{
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return Bar_32bit::Memory_type::get(_conf()) ==
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Bar_32bit::Memory_type::SIZE_64BIT;
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}
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bool prefetchable() {
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return Bar_32bit::Memory_prefetchable::get(_conf()); }
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Genode::size_t size()
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{
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return 1 + (memory() ? ~Bar_32bit::Memory_base::masked(_conf())
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: ~Bar_32bit::Io_base::masked(_conf()));
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}
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Genode::uint64_t addr()
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{
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if (memory())
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return (bit64()
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? ((Genode::uint64_t)read<Upper_bits>()<<32) : 0UL)
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| Bar_32bit::Memory_base::masked(read<Bar_32bit>());
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else
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return Bar_32bit::Io_base::masked(read<Bar_32bit>());
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}
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void set(Genode::uint64_t v)
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{
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if (!valid() || v == addr())
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return;
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if (memory()) {
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if (bit64())
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_get_and_set<Upper_bits>((Upper_bits::access_t)(v >> 32));
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_get_and_set<Bar_32bit>(Bar_32bit::Memory_base::masked(v & ~0U));
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} else
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_get_and_set<Bar_32bit>(Bar_32bit::Io_base::masked(v & ~0U));
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}
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};
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enum Base_addresses {
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BASE_ADDRESS_0 = 0x10,
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BASE_ADDRESS_COUNT_TYPE_0 = 6,
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BASE_ADDRESS_COUNT_TYPE_1 = 2,
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};
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struct Capability_pointer : Register<0x34, 8> {};
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struct Irq_line : Register<0x3c, 8>
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{
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enum { UNKNOWN = 0xff };
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};
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struct Irq_pin : Register<0x3d, 8>
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{
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enum { NO_INT = 0, INTA, INTB, INTC, INTD };
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};
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/**********************
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** PCI Capabilities **
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**********************/
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struct Pci_capability : Genode::Mmio
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{
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struct Id : Register<0,8>
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{
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enum {
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POWER_MANAGEMENT = 0x1,
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AGP = 0x2,
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VITAL_PRODUCT = 0x3,
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MSI = 0x5,
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VENDOR = 0x9,
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DEBUG = 0xa,
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BRIDGE_SUB = 0xd,
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PCI_E = 0x10,
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MSI_X = 0x11,
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SATA = 0x12,
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ADVANCED = 0x13,
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};
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};
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struct Pointer : Register<1,8> {};
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using Genode::Mmio::Mmio;
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};
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struct Power_management_capability : Pci_capability
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{
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struct Capabilities : Register<0x2, 16> {};
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struct Control_status : Register<0x4, 16>
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{
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struct Power_state : Bitfield<0, 2>
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{
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enum { D0, D1, D2, D3 };
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};
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struct No_soft_reset : Bitfield<3, 1> {};
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struct Pme_status : Bitfield<15,1> {};
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};
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struct Data : Register<0x7, 8> {};
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using Pci_capability::Pci_capability;
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bool power_on(Delayer & delayer)
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{
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using Reg = Control_status::Power_state;
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if (read<Reg>() == Reg::D0)
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return false;
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write<Reg>(Reg::D0);
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/*
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* PCI Express 4.3 - 5.3.1.4. D3 State
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*
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* "Unless Readiness Notifications mechanisms are used ..."
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* "a minimum recovery time following a D3 hot → D0 transition of"
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* "at least 10 ms ..."
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*/
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delayer.usleep(10'000);
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return true;
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}
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void power_off()
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{
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using Reg = Control_status::Power_state;
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if (read<Reg>() != Reg::D3) write<Reg>(Reg::D3);
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}
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bool soft_reset()
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{
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return !read<Control_status::No_soft_reset>();
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}
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};
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struct Msi_capability : Pci_capability
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{
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struct Control : Register<0x2, 16>
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{
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struct Enable : Bitfield<0,1> {};
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struct Multi_message_capable : Bitfield<1,3> {};
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struct Multi_message_enable : Bitfield<4,3> {};
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struct Large_address_capable : Bitfield<7,1> {};
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};
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struct Address_32 : Register<0x4, 32> {};
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struct Data_32 : Register<0x8, 16> {};
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struct Address_64_lower : Register<0x4, 32> {};
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struct Address_64_upper : Register<0x8, 32> {};
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struct Data_64 : Register<0xc, 16> {};
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using Pci_capability::Pci_capability;
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void enable(Genode::addr_t address,
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Genode::uint16_t data)
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{
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if (read<Control::Large_address_capable>()) {
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Genode::uint64_t addr = address;
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write<Address_64_upper>((Genode::uint32_t)(addr >> 32));
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write<Address_64_lower>((Genode::uint32_t)addr);
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write<Data_64>(data);
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} else {
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write<Address_32>((Genode::uint32_t)address);
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write<Data_32>(data);
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}
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write<Control::Enable>(1);
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};
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};
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struct Msi_x_capability : Pci_capability
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{
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struct Control : Register<0x2, 16>
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{
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struct Slots : Bitfield<0, 10> {};
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struct Size : Bitfield<0, 11> {};
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struct Function_mask : Bitfield<14, 1> {};
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struct Enable : Bitfield<15, 1> {};
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};
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struct Table : Register<0x4, 32>
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{
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struct Bar_index : Bitfield<0, 3> {};
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struct Offset : Bitfield<3, 29> {};
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};
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struct Pending_bit_array : Register<0x8, 32>
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{
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struct Bar_index : Bitfield<0, 3> {};
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struct Offset : Bitfield<3, 29> {};
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};
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struct Table_entry : Genode::Mmio
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{
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enum { SIZE = 16 };
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struct Address_64_lower : Register<0x0, 32> { };
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struct Address_64_upper : Register<0x4, 32> { };
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struct Data : Register<0x8, 32> { };
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struct Vector_control : Register<0xc, 32>
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{
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struct Mask : Bitfield <0, 1> { };
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};
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using Genode::Mmio::Mmio;
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};
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using Pci_capability::Pci_capability;
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Genode::uint8_t bar() {
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return (Genode::uint8_t) read<Table::Bar_index>(); }
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Genode::size_t table_offset() {
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return read<Table::Offset>() << 3; }
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unsigned slots() { return read<Control::Slots>(); }
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void enable()
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{
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Control::access_t ctrl = read<Control>();
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Control::Function_mask::set(ctrl, 0);
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Control::Enable::set(ctrl, 1);
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write<Control>(ctrl);
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}
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};
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struct Pci_express_capability : Pci_capability
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{
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struct Capabilities : Register<0x2, 16> {};
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struct Device_capabilities : Register<0x4, 32>
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{
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struct Function_level_reset : Bitfield<28,1> {};
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};
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struct Device_control : Register<0x8, 16>
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{
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struct Function_level_reset : Bitfield<15,1> {};
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};
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struct Device_status : Register<0xa, 16>
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{
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struct Correctable_error : Bitfield<0, 1> {};
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struct Non_fatal_error : Bitfield<1, 1> {};
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struct Fatal_error : Bitfield<2, 1> {};
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struct Unsupported_request : Bitfield<3, 1> {};
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struct Aux_power : Bitfield<4, 1> {};
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struct Transactions_pending : Bitfield<5, 1> {};
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};
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struct Link_capabilities : Register<0xc, 32>
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{
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struct Max_link_speed : Bitfield<0, 4> {};
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};
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struct Link_control : Register<0x10, 16>
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{
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struct Lbm_irq_enable : Bitfield<10,1> {};
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};
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struct Link_status : Register<0x12, 16>
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{
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struct Lbm_status : Bitfield<10,1> {};
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};
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struct Slot_capabilities : Register<0x14, 32> {};
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struct Slot_control : Register<0x18, 16> {};
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struct Slot_status : Register<0x1a, 16> {};
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struct Root_control : Register<0x1c, 16>
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{
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struct Pme_irq_enable : Bitfield<3,1> {};
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};
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struct Root_status : Register<0x20, 32>
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{
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struct Pme : Bitfield<16,1> {};
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};
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struct Device_capabilities_2 : Register<0x24, 32> {};
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struct Device_control_2 : Register<0x28, 16> {};
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struct Device_status_2 : Register<0x2a, 16> {};
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struct Link_capabilities_2 : Register<0x2c, 32> {};
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struct Link_control_2 : Register<0x30, 16>
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{
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struct Link_speed : Bitfield<0, 4> {};
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};
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struct Link_status_2 : Register<0x32, 16> {};
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struct Slot_capabilities_2 : Register<0x34, 32> {};
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struct Slot_control_2 : Register<0x38, 16> {};
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struct Slot_status_2 : Register<0x3a, 16> {};
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using Pci_capability::Pci_capability;
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void power_management_event_enable()
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{
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write<Root_status::Pme>(1);
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write<Root_control::Pme_irq_enable>(1);
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};
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void clear_dev_errors()
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{
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Device_status::access_t v = read<Device_status>();
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Device_status::Correctable_error::set(v,1);
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Device_status::Non_fatal_error::set(v,1);
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Device_status::Fatal_error::set(v,1);
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Device_status::Unsupported_request::set(v,1);
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Device_status::Aux_power::set(v,1);
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write<Device_status>(v);
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}
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void link_bandwidth_management_enable()
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{
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write<Link_status::Lbm_status>(1);
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write<Link_control::Lbm_irq_enable>(1);
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}
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void reset(Delayer & delayer)
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{
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if (!read<Device_capabilities::Function_level_reset>())
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return;
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write<Device_control::Function_level_reset>(1);
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try {
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wait_for(Attempts(100), Microseconds(10000), delayer,
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Device_status::Transactions_pending::Equal(0));
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} catch(Polling_timeout) { }
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}
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};
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/*********************************
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** PCI-E extended capabilities **
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*********************************/
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enum { PCI_E_EXTENDED_CAPS_OFFSET = 0x100U };
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struct Pci_express_extended_capability : Genode::Mmio
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{
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struct Id : Register<0x0, 16>
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{
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enum {
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INVALID = 0x0,
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ADVANCED_ERROR_REPORTING = 0x1,
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VIRTUAL_CHANNEL = 0x2,
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DEVICE_SERIAL_NUMBER = 0x3,
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POWER_BUDGETING = 0x4,
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VENDOR = 0xb,
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MULTI_ROOT_IO_VIRT = 0x11,
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};
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};
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struct Next_and_version : Register<0x2, 16>
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{
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struct Offset : Bitfield<4, 12> {};
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};
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using Genode::Mmio::Mmio;
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};
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struct Advanced_error_reporting_capability : Pci_express_extended_capability
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{
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struct Uncorrectable_error_status : Register<0x4, 32> {};
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struct Correctable_error_status : Register<0x10, 32> {};
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struct Root_error_command : Register<0x2c, 32>
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{
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struct Correctable_error_enable : Bitfield<0,1> {};
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struct Non_fatal_error_enable : Bitfield<1,1> {};
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struct Fatal_error_enable : Bitfield<2,1> {};
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};
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struct Root_error_status : Register<0x30, 32> {};
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using Pci_express_extended_capability::Pci_express_extended_capability;
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void enable()
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{
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Root_error_command::access_t v = 0;
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Root_error_command::Correctable_error_enable::set(v,1);
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Root_error_command::Non_fatal_error_enable::set(v,1);
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Root_error_command::Fatal_error_enable::set(v,1);
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write<Root_error_command>(v);
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};
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void clear()
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{
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write<Root_error_status>(read<Root_error_status>());
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write<Correctable_error_status>(read<Correctable_error_status>());
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write<Uncorrectable_error_status>(read<Uncorrectable_error_status>());
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};
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};
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Genode::Constructible<Power_management_capability> power_cap {};
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Genode::Constructible<Msi_capability> msi_cap {};
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Genode::Constructible<Msi_x_capability> msi_x_cap {};
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Genode::Constructible<Pci_express_capability> pci_e_cap {};
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Genode::Constructible<Advanced_error_reporting_capability> adv_err_cap {};
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Base_address bar0 { base() + BASE_ADDRESS_0 };
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Base_address bar1 { base() + BASE_ADDRESS_0 + 0x4 };
|
|
|
|
void clear_errors() {
|
|
if (adv_err_cap.constructed()) adv_err_cap->clear(); }
|
|
|
|
void scan()
|
|
{
|
|
using namespace Genode;
|
|
|
|
if (!read<Status::Capabilities>())
|
|
return;
|
|
|
|
uint16_t off = read<Capability_pointer>();
|
|
while (off) {
|
|
Pci_capability cap(base() + off);
|
|
switch(cap.read<Pci_capability::Id>()) {
|
|
case Pci_capability::Id::POWER_MANAGEMENT:
|
|
power_cap.construct(base()+off); break;
|
|
case Pci_capability::Id::MSI:
|
|
msi_cap.construct(base()+off); break;
|
|
case Pci_capability::Id::MSI_X:
|
|
msi_x_cap.construct(base()+off); break;
|
|
case Pci_capability::Id::PCI_E:
|
|
pci_e_cap.construct(base()+off); break;
|
|
|
|
default:
|
|
/* ignore unhandled capability */ ;
|
|
}
|
|
off = cap.read<Pci_capability::Pointer>();
|
|
}
|
|
|
|
if (!pci_e_cap.constructed())
|
|
return;
|
|
|
|
off = PCI_E_EXTENDED_CAPS_OFFSET;
|
|
while (off) {
|
|
Pci_express_extended_capability cap(base() + off);
|
|
switch (cap.read<Pci_express_extended_capability::Id>()) {
|
|
case Pci_express_extended_capability::Id::INVALID:
|
|
return;
|
|
case Pci_express_extended_capability::Id::ADVANCED_ERROR_REPORTING:
|
|
adv_err_cap.construct(base() + off); break;
|
|
|
|
default:
|
|
/* ignore unhandled extended capability */ ;
|
|
}
|
|
off = cap.read<Pci_express_extended_capability::Next_and_version::Offset>();
|
|
}
|
|
}
|
|
|
|
using Genode::Mmio::Mmio;
|
|
|
|
bool valid() {
|
|
return read<Vendor>() != Vendor::INVALID; }
|
|
|
|
bool bridge()
|
|
{
|
|
return read<Header_type::Type>() == 1 ||
|
|
read<Base_class_code>() == Base_class_code::BRIDGE;
|
|
}
|
|
|
|
template <typename MEM_FN, typename IO_FN>
|
|
void for_each_bar(MEM_FN const & memory, IO_FN const & io)
|
|
{
|
|
Genode::addr_t const reg_addr = base() + BASE_ADDRESS_0;
|
|
Genode::size_t const reg_cnt =
|
|
(read<Header_type::Type>()) ? BASE_ADDRESS_COUNT_TYPE_1
|
|
: BASE_ADDRESS_COUNT_TYPE_0;
|
|
|
|
for (unsigned i = 0; i < reg_cnt; i++) {
|
|
Base_address reg0(reg_addr + i*0x4);
|
|
if (!reg0.valid())
|
|
continue;
|
|
if (reg0.memory()) {
|
|
memory(reg0.addr(), reg0.size(), i, reg0.prefetchable());
|
|
if (reg0.bit64()) i++;
|
|
} else
|
|
io(reg0.addr(), reg0.size(), i);
|
|
}
|
|
};
|
|
|
|
void set_bar_address(unsigned idx, Genode::uint64_t addr)
|
|
{
|
|
if (idx > 5 || (idx > 1 && bridge()))
|
|
return;
|
|
|
|
Base_address bar { base() + BASE_ADDRESS_0 + idx*0x4 };
|
|
bar.set(addr);
|
|
}
|
|
|
|
void power_on(Delayer & delayer)
|
|
{
|
|
if (!power_cap.constructed() || !power_cap->power_on(delayer))
|
|
return;
|
|
|
|
if (power_cap->soft_reset() && pci_e_cap.constructed())
|
|
pci_e_cap->reset(delayer);
|
|
}
|
|
|
|
void power_off()
|
|
{
|
|
if (power_cap.constructed()) power_cap->power_off();
|
|
}
|
|
};
|
|
|
|
|
|
struct Pci::Config_type0 : Pci::Config
|
|
{
|
|
struct Expansion_rom_base_addr : Register<0x30, 32> {};
|
|
|
|
using Pci::Config::Config;
|
|
|
|
Base_address bar2 { base() + BASE_ADDRESS_0 + 0x8 };
|
|
Base_address bar3 { base() + BASE_ADDRESS_0 + 0xc };
|
|
Base_address bar4 { base() + BASE_ADDRESS_0 + 0x10 };
|
|
Base_address bar5 { base() + BASE_ADDRESS_0 + 0x14 };
|
|
|
|
struct Subsystem_vendor : Register<0x2c, 16> { };
|
|
struct Subsystem_device : Register<0x2e, 16> { };
|
|
};
|
|
|
|
|
|
struct Pci::Config_type1 : Pci::Config
|
|
{
|
|
struct Sec_lat_timer_bus : Register<0x18, 32>
|
|
{
|
|
struct Primary_bus : Bitfield<0, 8> {};
|
|
struct Secondary_bus : Bitfield<8, 8> {};
|
|
struct Sub_bus : Bitfield<16, 8> {};
|
|
};
|
|
|
|
struct Io_base_limit : Register<0x1c, 16> {};
|
|
|
|
struct Memory_base : Register<0x20, 16> {};
|
|
struct Memory_limit : Register<0x22, 16> {};
|
|
|
|
struct Prefetchable_memory_base : Register<0x24, 32> {};
|
|
struct Prefetchable_memory_base_upper : Register<0x28, 32> {};
|
|
struct Prefetchable_memory_limit_upper : Register<0x2c, 32> {};
|
|
|
|
struct Io_base_limit_upper : Register<0x30, 32> {};
|
|
|
|
struct Expansion_rom_base_addr : Register<0x38, 32> {};
|
|
|
|
struct Bridge_control : Register<0x3e, 16>
|
|
{
|
|
struct Serror : Bitfield<1, 1> {};
|
|
};
|
|
|
|
using Pci::Config::Config;
|
|
|
|
bus_t primary_bus_number() {
|
|
return (bus_t) read<Sec_lat_timer_bus::Primary_bus>(); }
|
|
|
|
bus_t secondary_bus_number() {
|
|
return (bus_t) read<Sec_lat_timer_bus::Secondary_bus>(); }
|
|
|
|
bus_t subordinate_bus_number() {
|
|
return (bus_t) read<Sec_lat_timer_bus::Sub_bus>(); }
|
|
};
|
|
|
|
#endif /* __INCLUDE__PCI__CONFIG_H__ */
|