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Mark Vels 1668983efa base-hw: RISC-V Rocket Core on Zynq 
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes
advantage of the new timer infrastructure introduced with the privileged 1.8 and
adds improved TLB flush support.

fixes #1880
2016-02-26 11:36:51 +01:00
..
base hw: remove main thread's initial UTCB from vm area 2015-12-10 13:16:27 +01:00
cap_session hw: kernel backed capabilities (Fix #1443) 2015-05-26 09:40:04 +02:00
cpu_session Move repositories to 'repos/' subdirectory 2014-05-14 16:08:00 +02:00
kernel hw: reference count capabilities in UTCBs 2015-12-10 13:16:25 +01:00
pd_session hw: kernel backed capabilities (Fix #1443) 2015-05-26 09:40:04 +02:00
signal_session hw: kernel backed capabilities (Fix #1443) 2015-05-26 09:40:04 +02:00
spec base-hw: RISC-V Rocket Core on Zynq 2016-02-26 11:36:51 +01:00
vm_session hw_arndale: enable ARM virtualization extensions 2015-02-27 11:48:05 +01:00