genode/repos/base/include/drivers/defs/imx7d_sabre.h
Stefan Kalkowski 6d48b5484d hw: correct the ARM cache maintainance operations
This commit fixes the following issues regarding cache maintainance
under ARM:

* read out I-, and D-cache line size at runtime and use the correct one
* remove 'update_data_region' call from unprivileged syscalls
* rename 'update_instr_region' syscall to 'cache_coherent_region' to
  reflect what it doing, namely make I-, and D-cache coherent
* restrict 'cache_coherent_region' syscall to one page at a time
* lookup the region given in a 'cache_coherent_region' syscall in the
  page-table of the PD to prevent machine exceptions in the kernel
* only clean D-cache lines, do not invalidate them when pages where
  added on Cortex-A8 and ARMv6 (MMU sees phys. memory here)
* remove unused code relicts of cache maintainance

In addition it introduces per architecture memory clearance functions
used by core, when preparing new dataspaces. Thereby, it optimizes:

* on ARMv7 using per-word assignments
* on ARMv8 using cacheline zeroing
* on x86_64 using 'rept stosq' assembler instruction

Fix #3685
2020-03-26 11:38:55 +01:00

44 lines
1.0 KiB
C++

/*
* \brief Definitions for the Imx7 dual sabre board
* \author Stefan Kalkowski
* \date 2018-10-07
*/
/*
* Copyright (C) 2018 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
#include <drivers/defs/arm_v7.h>
namespace Imx7d_sabre {
using namespace Arm_v7;
enum {
RAM_0_BASE = 0x80000000UL,
RAM_0_SIZE = 0x40000000UL,
IRQ_CONTROLLER_BASE = 0x31000000UL,
IRQ_CONTROLLER_SIZE = 0x8000,
SRC_MMIO_BASE = 0x30390000UL,
AIPS_1_MMIO_BASE = 0x301f0000UL,
AIPS_2_MMIO_BASE = 0x305f0000UL,
AIPS_3_MMIO_BASE = 0x309f0000UL,
UART_1_MMIO_BASE = 0x30860000UL,
UART_1_MMIO_SIZE = 0x10000UL,
TIMER_CLOCK = 1000000000UL,
};
}
#endif /* _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_ */