genode/base/include/arm/cpu/cpu_state.h
Stefan Kalkowski 8393ac6895 base-hw: implement vm_session for TrustZone
* Introduces Schedule_context
* Use fast-interrupts or normal interrupts
* Add mode-transition between secure/non-secure world
* Limit system resources for Genode apps due to non-secure world

This commit implements the newly introduced Vm session interface to be used
on top of TrustZone capable Armv7 CPUs. Therefore a new Schedule_context is
introduced in the kernel. Threads and Vms are both Schedule_contexts used
by the scheduler. In contrast to a thread a vm uses a different assembler
mode switch to the non-secure, virtual world, as well as another exception
is used, when the non-secure world is left. For both worlds to co-exist
the interrupt-controller needs to be configured, so that the secure (Genode)
world uses fast-interrupts only, and the non-secure world only legacy
interrupts.
The only TrustZone capable platform the base-hw kernel works on top of
is the CoreTile Express 9x4 for the Versatile Express motherboard. For a
virtual machine working properly on top some platform resources must be
reserved. Therefore there exist two flavours of this platform now, one with
the 'trustzone' spec-variable enabled, and one without. If 'trustzone' is
specified most platform resources (DDR-RAM, and most IRQs) are reserved
for the Vm and not available to the secure Genode world.
2012-10-29 10:08:30 +01:00

76 lines
1.7 KiB
C++

/*
* \brief CPU state
* \author Norman Feske
* \author Stefan Kalkowski
* \date 2011-05-06
*/
/*
* Copyright (C) 2011-2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM__CPU__CPU_STATE_H_
#define _INCLUDE__ARM__CPU__CPU_STATE_H_
#include <base/stdint.h>
namespace Genode {
struct Cpu_state
{
/**
* Native exception types
*/
enum Cpu_exception {
RESET,
UNDEFINED_INSTRUCTION,
SUPERVISOR_CALL,
PREFETCH_ABORT,
DATA_ABORT,
INTERRUPT_REQUEST,
FAST_INTERRUPT_REQUEST,
MAX_CPU_EXCEPTION,
};
enum { MAX_GPR = 13 };
addr_t r[MAX_GPR]; /* r0-r12 - general purpose */
addr_t sp; /* r13 - stack pointer */
addr_t lr; /* r14 - link register */
addr_t ip; /* r15 - instruction pointer */
addr_t cpsr; /* current program status register */
Cpu_exception cpu_exception; /* last exception */
};
struct Cpu_state_modes : Cpu_state
{
/**
* Common banked registers for exception modes
*/
struct Mode_state {
enum Mode {
UND, /* Undefined */
SVC, /* Supervisor */
ABORT, /* Abort */
IRQ, /* Interrupt */
FIQ, /* Fast Interrupt */
MAX
};
addr_t spsr; /* saved program status register */
addr_t sp; /* banked stack pointer */
addr_t lr; /* banked link register */
};
Mode_state mode[Mode_state::MAX]; /* exception mode registers */
addr_t fiq_r[5]; /* fast-interrupt mode r8-r12 */
};
}
#endif /* _INCLUDE__ARM__CPU__CPU_STATE_H_ */