mirror of
https://github.com/genodelabs/genode.git
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291 lines
8.9 KiB
C++
291 lines
8.9 KiB
C++
/*
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* \brief VirtIO PCI device
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* \author Piotr Tworek
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* \date 2019-09-27
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*/
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/*
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* Copyright (C) 2020 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__VIRTIO__PCI_DEVICE_H_
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#define _INCLUDE__VIRTIO__PCI_DEVICE_H_
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#include <os/attached_mmio.h>
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#include <irq_session/client.h>
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#include <legacy/x86/platform_device/client.h>
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#include <legacy/x86/platform_session/connection.h>
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#include <virtio/queue.h>
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namespace Virtio {
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using namespace Genode;
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struct Device_mmio;
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class Device;
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}
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struct Virtio::Device_mmio : public Attached_mmio
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{
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struct DeviceFeatureSelect : Register<0x00, 32> { };
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struct DeviceFeature : Register<0x04, 32> { };
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struct DriverFeatureSelect : Register<0x08, 32> { };
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struct DriverFeature : Register<0x0C, 32> { };
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struct MsiXConfig : Register<0x10, 16> { };
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struct NumQueues : Register<0x12, 16> { };
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struct DeviceStatus : Register<0x14, 8> { };
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struct ConfigGeneration : Register<0x15, 8> { };
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struct QueueSelect : Register<0x16, 16> { };
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struct QueueSize : Register<0x18, 16> { };
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struct QueueMsixVector : Register<0x1A, 16> { };
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struct QueueEnable : Register<0x1C, 16> { };
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struct QueueNotifyOff : Register<0x1E, 16> { };
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struct QueueDescLow : Register<0x20, 32> { };
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struct QueueDescHigh : Register<0x24, 32> { };
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struct QueueAvailLow : Register<0x28, 32> { };
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struct QueueAvailHigh : Register<0x2C, 32> { };
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struct QueueUsedLow : Register<0x30, 32> { };
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struct QueueUsedHigh : Register<0x34, 32> { };
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struct Config_8 : Register_array<0x0, 8, 256, 8> { };
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struct Config_16 : Register_array<0x0, 16, 128, 16> { };
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struct Config_32 : Register_array<0x0, 32, 64, 32> { };
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struct IrqReason : Register<0x0, 32> { };
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Device_mmio(Genode::Env &env,
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Genode::addr_t base,
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Genode::size_t size)
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: Attached_mmio(env, base, size, false) { }
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};
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class Virtio::Device
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{
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public:
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struct Configuration_failed : Genode::Exception { };
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enum Status : uint8_t
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{
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RESET = 0,
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ACKNOWLEDGE = 1 << 0,
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DRIVER = 1 << 1,
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DRIVER_OK = 1 << 2,
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FEATURES_OK = 1 << 3,
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FAILED = 1 << 7,
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};
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enum Access_size : uint8_t
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{
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ACCESS_8BIT,
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ACCESS_16BIT,
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ACCESS_32BIT,
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};
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private:
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/*
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* Noncopyable
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*/
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Device(Device const &) = delete;
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Device &operator = (Device const &) = delete;
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enum {
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VIRTIO_PCI_BASE_ID = 0x1040,
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VIRTIO_MSI_NO_VECTOR = 0xffff
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};
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Genode::Env &_env;
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Platform::Device_client &_device;
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Genode::Irq_session_client _irq { _device.irq(0) };
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uint32_t _notify_offset_multiplier = 0;
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Genode::Constructible<Device_mmio> _cfg_common { };
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Genode::Constructible<Device_mmio> _dev_config { };
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Genode::Constructible<Device_mmio> _notify { };
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Genode::Constructible<Device_mmio> _isr { };
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void _configure()
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{
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typedef Platform::Device Pdev;
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enum { PCI_STATUS = 0x6, PCI_CAPABILITIES = 0x34, };
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auto status = _device.config_read(PCI_STATUS, Pdev::ACCESS_16BIT);
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if (!(status & 0x10)) {
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error("PCI capabilities missing according to device status!");
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throw Configuration_failed();
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}
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auto addr = _device.config_read(PCI_CAPABILITIES, Pdev::ACCESS_8BIT);
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addr &= 0xFC;
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while (addr) {
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enum { ID_VNDR = 0x09 };
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enum { CAP_ID = 0, CAP_LIST_NEXT = 1 };
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auto const cap_id = _device.config_read(addr + CAP_ID, Pdev::ACCESS_8BIT);
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auto const cap_next = _device.config_read(addr + CAP_LIST_NEXT, Pdev::ACCESS_8BIT);
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if (cap_id == ID_VNDR) {
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enum { CFG_TYPE = 0x3, BAR = 0x4, OFFSET = 0x8,
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LENGTH = 0xC, NOTIFY_OFFSET_MULT = 0x10 };
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enum { COMMON_CFG = 1, NOTIFY_CFG = 2, ISR_CFG = 3,
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DEVICE_CFG = 4, PCI_CFG = 5 };
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auto const cfg_type = _device.config_read(addr + CFG_TYPE, Pdev::ACCESS_8BIT);
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auto const bar = _device.config_read(addr + BAR, Pdev::ACCESS_8BIT);
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auto const off = _device.config_read(addr + OFFSET, Pdev::ACCESS_32BIT);
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auto const len = _device.config_read(addr + LENGTH, Pdev::ACCESS_32BIT);
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if (cfg_type == COMMON_CFG) {
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auto const r = _device.resource(bar);
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_cfg_common.construct(_env, r.base() + off, len);
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} else if (cfg_type == DEVICE_CFG) {
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auto const r = _device.resource(bar);
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_dev_config.construct(_env, r.base() + off, len);
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} else if (cfg_type == NOTIFY_CFG) {
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_notify_offset_multiplier = _device.config_read(
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addr + NOTIFY_OFFSET_MULT, Pdev::ACCESS_32BIT);
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auto const r = _device.resource(bar);
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_notify.construct(_env, r.base() + off, len);
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} else if (cfg_type == ISR_CFG) {
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auto const r = _device.resource(bar);
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_isr.construct(_env, r.base() + off, len);
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}
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}
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addr = cap_next;
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}
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if (!_cfg_common.constructed() || !_dev_config.constructed() ||
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!_notify.constructed() || !_isr.constructed()) {
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error("Required VirtIO PCI capabilities not found!");
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throw Configuration_failed();
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}
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_cfg_common->write<Device_mmio::MsiXConfig>(VIRTIO_MSI_NO_VECTOR);
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}
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public:
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Device(Genode::Env &env,
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Platform::Device_client device)
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: _env(env), _device(device)
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{
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_configure();
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}
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uint32_t vendor_id() { return _device.vendor_id(); }
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uint32_t device_id() {
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return _device.device_id() - VIRTIO_PCI_BASE_ID; }
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uint8_t get_status() {
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return _cfg_common->read<Device_mmio::DeviceStatus>(); }
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bool set_status(uint8_t status)
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{
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_cfg_common->write<Device_mmio::DeviceStatus>(status);
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return _cfg_common->read<Device_mmio::DeviceStatus>() == status;
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}
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uint32_t get_features(uint32_t selection)
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{
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_cfg_common->write<Device_mmio::DeviceFeatureSelect>(selection);
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return _cfg_common->read<Device_mmio::DeviceFeature>();
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}
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void set_features(uint32_t selection, uint32_t features)
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{
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_cfg_common->write<Device_mmio::DriverFeatureSelect>(selection);
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_cfg_common->write<Device_mmio::DriverFeature>(features);
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}
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uint8_t get_config_generation() {
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return _cfg_common->read<Device_mmio::ConfigGeneration>(); }
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uint16_t get_max_queue_size(uint16_t queue_index)
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{
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_cfg_common->write<Device_mmio::QueueSelect>(queue_index);
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return _cfg_common->read<Device_mmio::QueueSize>();
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}
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uint32_t read_config(uint8_t offset, Access_size size)
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{
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switch (size) {
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case Device::ACCESS_8BIT:
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return _dev_config->read<Device_mmio::Config_8>(offset);
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case Device::ACCESS_16BIT:
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return _dev_config->read<Device_mmio::Config_16>(offset >> 1);
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case Device::ACCESS_32BIT:
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return _dev_config->read<Device_mmio::Config_32>(offset >> 2);
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}
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return 0;
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}
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void write_config(uint8_t offset, Access_size size, uint32_t value)
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{
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switch (size) {
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case Device::ACCESS_8BIT:
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_dev_config->write<Device_mmio::Config_8>(value, offset);
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break;
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case Device::ACCESS_16BIT:
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_dev_config->write<Device_mmio::Config_16>(value, offset >> 1);
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break;
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case Device::ACCESS_32BIT:
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_dev_config->write<Device_mmio::Config_32>(value, offset >> 2);
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break;
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}
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}
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bool configure_queue(uint16_t queue_index, Virtio::Queue_description desc)
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{
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_cfg_common->write<Device_mmio::QueueSelect>(queue_index);
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if (_cfg_common->read<Device_mmio::QueueEnable>()) {
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warning("VirtIO queues can't be re-configured after being enabled!");
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return false;
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}
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_cfg_common->write<Device_mmio::QueueMsixVector>(VIRTIO_MSI_NO_VECTOR);
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if (_cfg_common->read<Device_mmio::QueueMsixVector>() != VIRTIO_MSI_NO_VECTOR) {
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error("Failed to disable MSI-X for queue ", queue_index);
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return false;
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}
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_cfg_common->write<Device_mmio::QueueSize>(desc.size);
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uint64_t addr = desc.desc;
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_cfg_common->write<Device_mmio::QueueDescLow>((uint32_t)addr);
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_cfg_common->write<Device_mmio::QueueDescHigh>((uint32_t)(addr >> 32));
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addr = desc.avail;
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_cfg_common->write<Device_mmio::QueueAvailLow>((uint32_t)addr);
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_cfg_common->write<Device_mmio::QueueAvailHigh>((uint32_t)(addr >> 32));
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addr = desc.used;
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_cfg_common->write<Device_mmio::QueueUsedLow>((uint32_t)addr);
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_cfg_common->write<Device_mmio::QueueUsedHigh>((uint32_t)(addr >> 32));
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_cfg_common->write<Device_mmio::QueueEnable>(1);
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return _cfg_common->read<Device_mmio::QueueEnable>() != 0;
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}
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void notify_buffers_available(uint16_t queue_index) {
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_cfg_common->write<Device_mmio::QueueSelect>(queue_index);
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auto const offset = _cfg_common->read<Device_mmio::QueueNotifyOff>();
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auto const addr = (offset * _notify_offset_multiplier >> 1) + 1;
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_notify->local_addr<uint16_t>()[addr] = queue_index;
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}
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uint32_t read_isr() {
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return _isr->read<Device_mmio::IrqReason>(); }
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void irq_sigh(Signal_context_capability cap) {
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_irq.sigh(cap); }
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void irq_ack() { _irq.ack_irq(); }
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};
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#endif /* _INCLUDE__VIRTIO__PCI_DEVICE_H_ */
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