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This patch changes the top-level directory layout as a preparatory step for improving the tools for managing 3rd-party source codes. The rationale is described in the issue referenced below. Issue #1082
180 lines
4.1 KiB
C++
180 lines
4.1 KiB
C++
/*
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* \brief Driver base for the PrimeCell UART PL011 Revision r1p3
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* \author Martin stein
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* \date 2011-10-17
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__UART__PL011_BASE_H_
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#define _INCLUDE__DRIVERS__UART__PL011_BASE_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Genode
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{
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/**
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* Driver base for the PrimeCell UART PL011 Revision r1p3
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*/
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class Pl011_base : Mmio
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{
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protected:
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enum { MAX_BAUD_RATE = 0xfffffff };
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/**
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* Data register
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*/
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struct Uartdr : public Register<0x00, 16>
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{
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struct Data : Bitfield<0,8> { };
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struct Fe : Bitfield<8,1> { };
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struct Pe : Bitfield<9,1> { };
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struct Be : Bitfield<10,1> { };
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struct Oe : Bitfield<11,1> { };
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};
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/**
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* Flag register
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*/
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struct Uartfr : public Register<0x18, 16>
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{
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struct Cts : Bitfield<0,1> { };
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struct Dsr : Bitfield<1,1> { };
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struct Dcd : Bitfield<2,1> { };
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struct Busy : Bitfield<3,1> { };
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struct Rxfe : Bitfield<4,1> { };
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struct Txff : Bitfield<5,1> { };
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struct Rxff : Bitfield<6,1> { };
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struct Txfe : Bitfield<7,1> { };
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struct Ri : Bitfield<8,1> { };
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};
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/**
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* Integer baud rate register
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*/
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struct Uartibrd : public Register<0x24, 16>
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{
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struct Ibrd : Bitfield<0,15> { };
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};
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/**
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* Fractional Baud Rate Register
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*/
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struct Uartfbrd : public Register<0x28, 8>
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{
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struct Fbrd : Bitfield<0,6> { };
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};
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/**
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* Line Control Register
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*/
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struct Uartlcrh : public Register<0x2c, 16>
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{
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struct Wlen : Bitfield<5,2> {
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enum {
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WORD_LENGTH_8BITS = 3,
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WORD_LENGTH_7BITS = 2,
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WORD_LENGTH_6BITS = 1,
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WORD_LENGTH_5BITS = 0,
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};
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};
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};
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/**
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* Control Register
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*/
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struct Uartcr : public Register<0x30, 16>
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{
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struct Uarten : Bitfield<0,1> { };
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struct Txe : Bitfield<8,1> { };
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struct Rxe : Bitfield<9,1> { };
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};
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/**
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* Interrupt Mask Set/Clear
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*/
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struct Uartimsc : public Register<0x38, 16>
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{
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struct Imsc : Bitfield<0,11> { };
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};
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/**
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* Idle until the device is ready for action
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*/
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void _wait_until_ready() { while (read<Uartfr::Busy>()) ; }
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public:
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/**
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* Constructor
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* \param base device MMIO base
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* \param clock device reference clock frequency
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* \param baud_rate targeted UART baud rate
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*/
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inline Pl011_base(addr_t const base, uint32_t const clock,
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uint32_t const baud_rate);
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/**
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* Send ASCII char 'c' over the UART interface
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*/
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inline void put_char(char const c);
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};
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}
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Genode::Pl011_base::Pl011_base(addr_t const base, uint32_t const clock,
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uint32_t const baud_rate) : Mmio(base)
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{
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write<Uartcr>(Uartcr::Uarten::bits(1) |
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Uartcr::Txe::bits(1) |
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Uartcr::Rxe::bits(1));
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/*
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* We can't print an error or throw C++ exceptions because we must expect
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* both to be uninitialized yet, so its better to hold the program counter
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* in here for debugging.
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*/
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if (baud_rate > MAX_BAUD_RATE) while(1) ;
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/*
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* Calculate fractional and integer part of baud rate divisor to initialize
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* IBRD and FBRD.
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*/
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uint32_t const adjusted_br = baud_rate << 4;
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double const divisor = (double)clock / adjusted_br;
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Uartibrd::access_t const ibrd = (Uartibrd::access_t)divisor;
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Uartfbrd::access_t const fbrd = (Uartfbrd::access_t)(((divisor - ibrd)
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* 64) + 0.5);
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write<Uartfbrd::Fbrd>(fbrd);
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write<Uartibrd::Ibrd>(ibrd);
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write<Uartlcrh::Wlen>(Uartlcrh::Wlen::WORD_LENGTH_8BITS);
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/* unmask all interrupts */
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write<Uartimsc::Imsc>(0);
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_wait_until_ready();
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}
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void Genode::Pl011_base::put_char(char const c)
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{
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/* wait as long as the transmission buffer is full */
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while (read<Uartfr::Txff>()) ;
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/* transmit character */
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write<Uartdr::Data>(c);
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_wait_until_ready();
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}
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#endif /* _INCLUDE__DRIVERS__UART__PL011_BASE_H_ */
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