Martin Stein 53156de9f4 base_hw & arm: Memory attributes and light caching. ...

Enable caches. Core is not cached by now. This is because kernel
creates core space and doesn't know any memory attributes by now.
Cacheable pages are cached write-through without write-allocate.

Caching and write-combining is not supported for IOMEM by now.

2012-11-14 16:36:51 +01:00

..

doc

Nested init on i.MX31 via base_hw. Rework base_hw.

2012-11-14 16:36:41 +01:00

include

base: Tell a mapping wether it maps IO memory.

2012-11-14 16:36:51 +01:00

lib/mk

Nested init on i.MX31 via base_hw. Rework base_hw.

2012-11-14 16:36:41 +01:00

mk

Nested init on i.MX31 via base_hw. Rework base_hw.

2012-11-14 16:36:41 +01:00

run

Nested init on i.MX31 via base_hw. Rework base_hw.

2012-11-14 16:36:41 +01:00

src

base_hw & arm: Memory attributes and light caching.

2012-11-14 16:36:51 +01:00