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6d48b5484d
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685
113 lines
2.8 KiB
C++
113 lines
2.8 KiB
C++
/*
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* \brief MMIO and IRQ definitions common to i.MX53 SoC
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__IMX53_H_
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#define _INCLUDE__DRIVERS__DEFS__IMX53_H_
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namespace Imx53 {
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enum {
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MMIO_BASE = 0x0,
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MMIO_SIZE = 0x70000000,
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RAM_BANK_0_BASE = 0x70000000,
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RAM_BANK_0_SIZE = 0x40000000,
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RAM_BANK_1_BASE = 0xb0000000,
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RAM_BANK_1_SIZE = 0x40000000,
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SDHC_IRQ = 1,
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SDHC_MMIO_BASE = 0x50004000,
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SDHC_MMIO_SIZE = 0x00004000,
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UART_1_IRQ = 31,
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UART_1_MMIO_BASE = 0x53fbc000,
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UART_1_MMIO_SIZE = 0x00004000,
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EPIT_1_IRQ = 40,
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EPIT_1_MMIO_BASE = 0x53fac000,
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EPIT_1_MMIO_SIZE = 0x00004000,
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EPIT_2_IRQ = 41,
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EPIT_2_MMIO_BASE = 0x53fb0000,
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EPIT_2_MMIO_SIZE = 0x00004000,
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GPIO1_MMIO_BASE = 0x53f84000,
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GPIO1_MMIO_SIZE = 0x4000,
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GPIO2_MMIO_BASE = 0x53f88000,
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GPIO2_MMIO_SIZE = 0x4000,
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GPIO3_MMIO_BASE = 0x53f8c000,
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GPIO3_MMIO_SIZE = 0x4000,
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GPIO4_MMIO_BASE = 0x53f90000,
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GPIO4_MMIO_SIZE = 0x4000,
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GPIO5_MMIO_BASE = 0x53fdc000,
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GPIO5_MMIO_SIZE = 0x4000,
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GPIO6_MMIO_BASE = 0x53fe0000,
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GPIO6_MMIO_SIZE = 0x4000,
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GPIO7_MMIO_BASE = 0x53fe4000,
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GPIO7_MMIO_SIZE = 0x4000,
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GPIO1_IRQL = 50,
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GPIO1_IRQH = 51,
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GPIO2_IRQL = 52,
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GPIO2_IRQH = 53,
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GPIO3_IRQL = 54,
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GPIO3_IRQH = 55,
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GPIO4_IRQL = 56,
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GPIO4_IRQH = 57,
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GPIO5_IRQL = 103,
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GPIO5_IRQH = 104,
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GPIO6_IRQL = 105,
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GPIO6_IRQH = 106,
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GPIO7_IRQL = 107,
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GPIO7_IRQH = 108,
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IRQ_CONTROLLER_BASE = 0x0fffc000,
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IRQ_CONTROLLER_SIZE = 0x00004000,
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AIPS_1_MMIO_BASE = 0x53f00000,
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AIPS_2_MMIO_BASE = 0x63f00000,
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IOMUXC_BASE = 0x53fa8000,
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IOMUXC_SIZE = 0x00004000,
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PWM2_BASE = 0x53fb8000,
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PWM2_SIZE = 0x00004000,
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IPU_BASE = 0x18000000,
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IPU_SIZE = 0x08000000,
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SRC_BASE = 0x53fd0000,
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SRC_SIZE = 0x00004000,
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CCM_BASE = 0x53FD4000,
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CCM_SIZE = 0x00004000,
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I2C_2_IRQ = 63,
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I2C_2_BASE = 0x63fc4000,
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I2C_2_SIZE = 0x00004000,
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I2C_3_IRQ = 64,
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I2C_3_BASE = 0x53fec000,
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I2C_3_SIZE = 0x00004000,
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IIM_BASE = 0x63f98000,
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IIM_SIZE = 0x00004000,
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CSU_BASE = 0x63f9c000,
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CSU_SIZE = 0x00001000,
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M4IF_BASE = 0x63fd8000,
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M4IF_SIZE = 0x00001000,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__IMX53_H_ */
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