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3daa94ff2e
This commit contains features and buf fixes: * Catch errors during resource allocation * Because Mesa tries to allocate fence (hardware) registers for each batch buffer execution, do not allocate new fences for buffer objects that are already fenced * Add support for global hardware status page. Each context additionally has a per-process hardware status page, which we used to set the global hardware status page during Vgpu switch. This was obviously wrong. There is only one global hardware status page (set once during initialization) and a distinct per-process page for contexts. * Write the sequence number of the currently executing batch buffer to dword 52 of the per-process hardware status page. We use the pipe line command with QW_WRITE (quad word write), GLOBAL_GTT_IVB disabled (address space is per-process address space), and STORE_DATA_INDEX enabled (write goes to offset of hardware status page). This command used to write to the scratch page. But Linux now uses the first reserved word of the per-process hardware status page. * Add Gen9+ WaEnableGapsTsvCreditFix workaround. This sets the "GAPS TSV Credit fix Enable" bit of the Arbiter control register (GARBCNTLREG) as described by the documentation this bit should be set by the BIOS but is not on most Gen9/9.5 platforms. Not setting this bit leads to random GPU hangs. * Increase the context size from 20 to 22 pages for Gen9. On Gen8 the hardware context is 20 pages (1 hardware status page + 19 ring context register pages). On Gen9 the size of the ring context registers has increased by two pages to 21 pages or 81.3125 KBytes as the IGD documentation states. * The logical ring size in the ring buffer control of the execlist context has to be programmed with number of pages - 1. So 0 is 1 page. We programmed the actual number of pages before, leading to ring buffer execution of NOOPs if page behind our ring buffer was empty or GPU hangs if there was data on the page. issue #4260 |
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