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6d48b5484d
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685
44 lines
1.0 KiB
C++
44 lines
1.0 KiB
C++
/*
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* \brief Definitions for the Imx7 dual sabre board
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* \author Stefan Kalkowski
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* \date 2018-10-07
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*/
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/*
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* Copyright (C) 2018 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
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#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
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#include <drivers/defs/arm_v7.h>
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namespace Imx7d_sabre {
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using namespace Arm_v7;
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enum {
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RAM_0_BASE = 0x80000000UL,
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RAM_0_SIZE = 0x40000000UL,
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IRQ_CONTROLLER_BASE = 0x31000000UL,
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IRQ_CONTROLLER_SIZE = 0x8000,
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SRC_MMIO_BASE = 0x30390000UL,
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AIPS_1_MMIO_BASE = 0x301f0000UL,
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AIPS_2_MMIO_BASE = 0x305f0000UL,
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AIPS_3_MMIO_BASE = 0x309f0000UL,
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UART_1_MMIO_BASE = 0x30860000UL,
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UART_1_MMIO_SIZE = 0x10000UL,
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TIMER_CLOCK = 1000000000UL,
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};
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}
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#endif /* _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_ */
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