mirror of
https://github.com/genodelabs/genode.git
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863 lines
23 KiB
C++
863 lines
23 KiB
C++
/*
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* \brief Genode VirtualBox SUPLib supplements
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* \author Alexander Boettcher
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* \author Norman Feske
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* \author Christian Helmuth
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*/
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/*
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* Copyright (C) 2013-2021 Genode Labs GmbH
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*
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* This file is distributed under the terms of the GNU General Public License
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* version 2.
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*/
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#ifndef _VIRTUALBOX__VCPU_H_
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#define _VIRTUALBOX__VCPU_H_
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/* Genode includes */
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#include <base/log.h>
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#include <rom_session/connection.h>
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#include <timer_session/connection.h>
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#include <vm_session/connection.h>
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#include <cpu/vcpu_state.h>
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/* VirtualBox includes */
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#include "PGMInternal.h" /* enable access to pgm.s.* */
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#include "HMInternal.h" /* enable access to hm.s.* */
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#include "CPUMInternal.h" /* enable access to cpum.s.* */
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#include <VBox/vmm/vm.h>
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#include <VBox/vmm/hm_svm.h>
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#include <VBox/err.h>
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#include <VBox/vmm/pdmapi.h>
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#include <iprt/time.h>
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/* Genode's VirtualBox includes */
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#include "sup.h"
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/* Genode libc pthread binding */
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#include <internal/pthread.h>
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#include <VBox/vmm/rem.h>
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/*
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* VirtualBox stores segment attributes in Intel format using a 32-bit
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* value. Genode represents the attributes in packed format using a 16-bit
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* value.
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*/
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static inline Genode::uint16_t sel_ar_conv_to_genode(Genode::uint32_t v)
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{
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return (v & 0xff) | ((v & 0x1f000) >> 4);
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}
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static inline Genode::uint32_t sel_ar_conv_from_genode(Genode::uint16_t v)
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{
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return (v & 0xff) | (((uint32_t )v << 4) & 0x1f000);
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}
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class Vcpu_handler : public Genode::List<Vcpu_handler>::Element
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{
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protected:
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static Genode::Vm_connection::Exit_config const _exit_config;
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Genode::Entrypoint _ep;
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Genode::Blockade _blockade_emt { };
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Genode::Semaphore _sem_handler;
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Genode::Vcpu_state *_state { nullptr };
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pthread_cond_t _cond_wait;
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pthread_mutex_t _mutex;
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/* information used for NPT/EPT handling */
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Genode::addr_t npt_ept_exit_addr { 0 };
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RTGCUINT npt_ept_errorcode { 0 };
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bool npt_ept_unmap { false };
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/* state machine between EMT and EP thread of a vCPU */
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enum { RUNNING, PAUSED, IRQ_WIN, NPT_EPT } _vm_state { PAUSED };
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enum { PAUSE_EXIT, RUN } _next_state { RUN };
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private:
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bool _irq_win = false;
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unsigned const _cpu_id;
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PVM _vm { nullptr };
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PVMCPU _vcpu { nullptr };
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unsigned int _last_inj_info = 0;
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unsigned int _last_inj_error = 0;
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enum {
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REQ_IRQWIN_EXIT = 0x1000U,
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IRQ_INJ_VALID_MASK = 0x80000000UL,
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IRQ_INJ_NONE = 0U,
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/*
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* Intel® 64 and IA-32 Architectures Software Developer’s Manual
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* Volume 3C, Chapter 24.4.2.
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* May 2012
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*/
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BLOCKING_BY_STI = 1U << 0,
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BLOCKING_BY_MOV_SS = 1U << 1,
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ACTIVITY_STATE_ACTIVE = 0U,
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INTERRUPT_STATE_NONE = 0U,
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};
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timespec add_timespec_ns(timespec a, uint64_t ns) const
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{
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enum { NSEC_PER_SEC = 1'000'000'000ull };
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long sec = a.tv_sec;
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while (a.tv_nsec >= NSEC_PER_SEC) {
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a.tv_nsec -= NSEC_PER_SEC;
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sec++;
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}
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while (ns >= NSEC_PER_SEC) {
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ns -= NSEC_PER_SEC;
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sec++;
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}
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long nsec = a.tv_nsec + ns;
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while (nsec >= NSEC_PER_SEC) {
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nsec -= NSEC_PER_SEC;
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sec++;
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}
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return timespec { sec, nsec };
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}
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protected:
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int map_memory(Genode::Vm_connection &vm_session,
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RTGCPHYS GCPhys, RTGCUINT vbox_fault_reason);
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Genode::addr_t _vm_exits = 0;
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Genode::addr_t _recall_skip = 0;
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Genode::addr_t _recall_req = 0;
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Genode::addr_t _recall_inv = 0;
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Genode::addr_t _recall_drop = 0;
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Genode::addr_t _irq_request = 0;
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Genode::addr_t _irq_inject = 0;
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Genode::addr_t _irq_drop = 0;
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struct {
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unsigned ctrl[2];
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} next_utcb;
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unsigned _ept_fault_addr_type;
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Genode::uint64_t * pdpte_map(VM *pVM, RTGCPHYS cr3);
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void switch_to_hw(PCPUMCTX pCtx)
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{
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using Genode::Vcpu_state;
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again:
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/* write FPU state */
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AssertCompile(sizeof(Vcpu_state::Fpu::State) >= sizeof(X86FXSTATE));
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_state->fpu.charge([&] (Vcpu_state::Fpu::State &fpu) {
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::memcpy(&fpu, pCtx->pXStateR3, sizeof(X86FXSTATE));
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});
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Assert(_vm_state == IRQ_WIN || _vm_state == PAUSED || _vm_state == NPT_EPT);
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Assert(_next_state == PAUSE_EXIT || _next_state == RUN);
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/* wake up vcpu ep handler */
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_sem_handler.up();
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/* wait for next exit */
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_blockade_emt.block();
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/* next time run - recall() may change this */
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_next_state = RUN;
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/* write FPU state of vCPU to pCtx */
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_state->fpu.with_state([&] (Vcpu_state::Fpu::State const &fpu) {
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::memcpy(pCtx->pXStateR3, &fpu, sizeof(X86FXSTATE));
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});
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_state->discharge();
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if (_vm_state == IRQ_WIN) {
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_irq_window_pthread();
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goto again;
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} else
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if (_vm_state == NPT_EPT) {
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if (npt_ept_unmap) {
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Genode::error("NPT/EPT unmap not supported - stop");
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while (true) {
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_blockade_emt.block();
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}
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}
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Genode::addr_t const gp_map_addr = npt_ept_exit_addr & ~((1UL << 12) - 1);
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int res = attach_memory_to_vm(gp_map_addr, npt_ept_errorcode);
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if (res == VINF_SUCCESS) {
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goto again;
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}
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}
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if (!(_vm_state == PAUSED || _vm_state == NPT_EPT))
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Genode::error("which state we are ? ", (int)_vm_state, " ", Genode::Thread::myself()->name());
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Assert(_vm_state == PAUSED || _vm_state == NPT_EPT);
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}
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void _default_handler()
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{
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if (_vm_state != RUNNING)
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Genode::error(__func__, " _vm_state=", (int)_vm_state, " exit_reason=", Genode::Hex(_state->exit_reason));
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Assert(_vm_state == RUNNING);
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Assert(_state->actv_state.value() == ACTIVITY_STATE_ACTIVE);
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Assert(!(_state->inj_info.value() & IRQ_INJ_VALID_MASK));
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_vm_exits ++;
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_vm_state = PAUSED;
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_blockade_emt.wakeup();
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}
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bool _recall_handler()
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{
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if (_vm_state != RUNNING)
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Genode::error(__func__, " _vm_state=", (int)_vm_state, " exit_reason=", Genode::Hex(_state->exit_reason));
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Assert(_vm_state == RUNNING);
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_vm_exits ++;
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_recall_inv ++;
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Assert(_state->actv_state.value() == ACTIVITY_STATE_ACTIVE);
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if (_state->inj_info.value() & IRQ_INJ_VALID_MASK) {
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Assert(_state->flags.value() & X86_EFL_IF);
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if (_state->intr_state.value() != INTERRUPT_STATE_NONE)
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Genode::log("intr state ", Genode::Hex(_state->intr_state.value()),
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" ", Genode::Hex(_state->intr_state.value() & 0xf));
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Assert(_state->intr_state.value() == INTERRUPT_STATE_NONE);
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if (!continue_hw_accelerated())
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_recall_drop ++;
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/* got recall during irq injection and the guest is ready for
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* delivery of IRQ - just continue */
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return /* no-wait */ false;
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}
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/* are we forced to go back to emulation mode ? */
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if (!continue_hw_accelerated()) {
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/* go back to emulation mode */
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_default_handler();
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return /* wait */ true;
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}
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/* check whether we have to request irq injection window */
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if (check_to_request_irq_window(_vcpu)) {
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_state->discharge();
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_state->inj_info.charge(_state->inj_info.value());
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_irq_win = true;
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return /* no-wait */ false;
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}
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_default_handler();
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return /* wait */ true;
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}
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inline bool vbox_to_state(VM *pVM, PVMCPU pVCpu)
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{
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typedef Genode::Vcpu_state::Range Range;
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PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
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_state->ip.charge(pCtx->rip);
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_state->sp.charge(pCtx->rsp);
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_state->ax.charge(pCtx->rax);
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_state->bx.charge(pCtx->rbx);
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_state->cx.charge(pCtx->rcx);
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_state->dx.charge(pCtx->rdx);
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_state->bp.charge(pCtx->rbp);
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_state->si.charge(pCtx->rsi);
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_state->di.charge(pCtx->rdi);
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_state->r8.charge(pCtx->r8);
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_state->r9.charge(pCtx->r9);
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_state->r10.charge(pCtx->r10);
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_state->r11.charge(pCtx->r11);
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_state->r12.charge(pCtx->r12);
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_state->r13.charge(pCtx->r13);
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_state->r14.charge(pCtx->r14);
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_state->r15.charge(pCtx->r15);
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_state->flags.charge(pCtx->rflags.u);
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_state->sysenter_cs.charge(pCtx->SysEnter.cs);
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_state->sysenter_sp.charge(pCtx->SysEnter.esp);
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_state->sysenter_ip.charge(pCtx->SysEnter.eip);
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_state->dr7.charge(pCtx->dr[7]);
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_state->cr0.charge(pCtx->cr0);
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_state->cr2.charge(pCtx->cr2);
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_state->cr3.charge(pCtx->cr3);
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_state->cr4.charge(pCtx->cr4);
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_state->idtr.charge(Range { .limit = pCtx->idtr.cbIdt,
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.base = pCtx->idtr.pIdt });
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_state->gdtr.charge(Range { .limit = pCtx->gdtr.cbGdt,
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.base = pCtx->gdtr.pGdt });
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_state->efer.charge(CPUMGetGuestEFER(pVCpu));
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/*
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* Update the PDPTE registers if necessary
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*
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* Intel manual sections 4.4.1 of Vol. 3A and 26.3.2.4 of Vol. 3C
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* indicate the conditions when this is the case. The following
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* code currently does not check if the recompiler modified any
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* CR registers, which means the update can happen more often
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* than really necessary.
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*/
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if (pVM->hm.s.vmx.fSupported &&
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CPUMIsGuestPagingEnabledEx(pCtx) &&
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CPUMIsGuestInPAEModeEx(pCtx)) {
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Genode::uint64_t *pdpte = pdpte_map(pVM, pCtx->cr3);
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_state->pdpte_0.charge(pdpte[0]);
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_state->pdpte_1.charge(pdpte[1]);
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_state->pdpte_2.charge(pdpte[2]);
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_state->pdpte_3.charge(pdpte[3]);
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}
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_state->star.charge(pCtx->msrSTAR);
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_state->lstar.charge(pCtx->msrLSTAR);
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_state->cstar.charge(pCtx->msrCSTAR);
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_state->fmask.charge(pCtx->msrSFMASK);
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_state->kernel_gs_base.charge(pCtx->msrKERNELGSBASE);
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/* from HMVMXR0.cpp */
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bool interrupt_pending = false;
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uint8_t tpr = 0;
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uint8_t pending_interrupt = 0;
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PDMApicGetTPR(pVCpu, &tpr, &interrupt_pending, &pending_interrupt);
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_state->tpr.charge(tpr);
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_state->tpr_threshold.charge(0);
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if (interrupt_pending) {
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const uint8_t pending_priority = (pending_interrupt >> 4) & 0xf;
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const uint8_t tpr_priority = (tpr >> 4) & 0xf;
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if (pending_priority <= tpr_priority)
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_state->tpr_threshold.charge(pending_priority);
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else
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_state->tpr_threshold.charge(tpr_priority);
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}
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{
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::uint64_t tsc_aux = 0;
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auto const rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX,
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&tsc_aux);
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Assert(rcStrict == VINF_SUCCESS);
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if (rcStrict == VINF_SUCCESS)
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_state->tsc_aux.charge(tsc_aux);
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}
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return true;
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}
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inline bool state_to_vbox(VM *pVM, PVMCPU pVCpu)
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{
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PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
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pCtx->rip = _state->ip.value();
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pCtx->rsp = _state->sp.value();
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pCtx->rax = _state->ax.value();
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pCtx->rbx = _state->bx.value();
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pCtx->rcx = _state->cx.value();
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pCtx->rdx = _state->dx.value();
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pCtx->rbp = _state->bp.value();
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pCtx->rsi = _state->si.value();
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pCtx->rdi = _state->di.value();
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pCtx->rflags.u = _state->flags.value();
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pCtx->r8 = _state->r8.value();
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pCtx->r9 = _state->r9.value();
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pCtx->r10 = _state->r10.value();
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pCtx->r11 = _state->r11.value();
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pCtx->r12 = _state->r12.value();
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pCtx->r13 = _state->r13.value();
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pCtx->r14 = _state->r14.value();
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pCtx->r15 = _state->r15.value();
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pCtx->dr[7] = _state->dr7.value();
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if (pCtx->SysEnter.cs != _state->sysenter_cs.value())
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CPUMSetGuestMsr(pVCpu, MSR_IA32_SYSENTER_CS, _state->sysenter_cs.value());
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if (pCtx->SysEnter.esp != _state->sysenter_sp.value())
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CPUMSetGuestMsr(pVCpu, MSR_IA32_SYSENTER_ESP, _state->sysenter_sp.value());
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if (pCtx->SysEnter.eip != _state->sysenter_ip.value())
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CPUMSetGuestMsr(pVCpu, MSR_IA32_SYSENTER_EIP, _state->sysenter_ip.value());
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if (pCtx->idtr.cbIdt != _state->idtr.value().limit ||
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pCtx->idtr.pIdt != _state->idtr.value().base)
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CPUMSetGuestIDTR(pVCpu, _state->idtr.value().base, _state->idtr.value().limit);
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if (pCtx->gdtr.cbGdt != _state->gdtr.value().limit ||
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pCtx->gdtr.pGdt != _state->gdtr.value().base)
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CPUMSetGuestGDTR(pVCpu, _state->gdtr.value().base, _state->gdtr.value().limit);
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CPUMSetGuestEFER(pVCpu, _state->efer.value());
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if (pCtx->cr0 != _state->cr0.value())
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CPUMSetGuestCR0(pVCpu, _state->cr0.value());
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if (pCtx->cr2 != _state->cr2.value())
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CPUMSetGuestCR2(pVCpu, _state->cr2.value());
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if (pCtx->cr3 != _state->cr3.value()) {
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CPUMSetGuestCR3(pVCpu, _state->cr3.value());
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VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
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}
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if (pCtx->cr4 != _state->cr4.value())
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CPUMSetGuestCR4(pVCpu, _state->cr4.value());
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if (pCtx->msrSTAR != _state->star.value())
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CPUMSetGuestMsr(pVCpu, MSR_K6_STAR, _state->star.value());
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if (pCtx->msrLSTAR != _state->lstar.value())
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CPUMSetGuestMsr(pVCpu, MSR_K8_LSTAR, _state->lstar.value());
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if (pCtx->msrCSTAR != _state->cstar.value())
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CPUMSetGuestMsr(pVCpu, MSR_K8_CSTAR, _state->cstar.value());
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if (pCtx->msrSFMASK != _state->fmask.value())
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CPUMSetGuestMsr(pVCpu, MSR_K8_SF_MASK, _state->fmask.value());
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if (pCtx->msrKERNELGSBASE != _state->kernel_gs_base.value())
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CPUMSetGuestMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, _state->kernel_gs_base.value());
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const uint32_t tpr = _state->tpr.value();
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/* reset message transfer descriptor for next invocation */
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Assert (!(_state->inj_info.value() & IRQ_INJ_VALID_MASK));
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next_utcb.ctrl[0] = _state->ctrl_primary.value();
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next_utcb.ctrl[1] = _state->ctrl_secondary.value();
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if (_state->intr_state.value() & 3) {
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_state->intr_state.charge(_state->intr_state.value());
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_state->actv_state.charge(ACTIVITY_STATE_ACTIVE);
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}
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VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
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|
||
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
|
||
pVCpu->cpum.s.fUseFlags |= (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_SINCE_REM);
|
||
|
||
if (_state->intr_state.value() != 0) {
|
||
Assert(_state->intr_state.value() == BLOCKING_BY_STI ||
|
||
_state->intr_state.value() == BLOCKING_BY_MOV_SS);
|
||
EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
|
||
} else
|
||
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
|
||
|
||
PDMApicSetTPR(pVCpu, tpr);
|
||
|
||
return true;
|
||
}
|
||
|
||
|
||
inline bool check_to_request_irq_window(PVMCPU pVCpu)
|
||
{
|
||
if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
|
||
return false;
|
||
|
||
if (!TRPMHasTrap(pVCpu) &&
|
||
!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC |
|
||
VMCPU_FF_INTERRUPT_PIC)))
|
||
return false;
|
||
|
||
_irq_request++;
|
||
|
||
unsigned const vector = 0;
|
||
_state->inj_info.charge(REQ_IRQWIN_EXIT | vector);
|
||
|
||
return true;
|
||
}
|
||
|
||
|
||
void _irq_window()
|
||
{
|
||
if (_vm_state != RUNNING)
|
||
Genode::error(__func__, " _vm_state=", (int)_vm_state, " exit_reason=", Genode::Hex(_state->exit_reason));
|
||
Assert(_vm_state == RUNNING);
|
||
|
||
_vm_exits ++;
|
||
|
||
_vm_state = IRQ_WIN;
|
||
_blockade_emt.wakeup();
|
||
}
|
||
|
||
void _npt_ept()
|
||
{
|
||
if (_vm_state != RUNNING)
|
||
Genode::error(__func__, " _vm_state=", (int)_vm_state, " exit_reason=", Genode::Hex(_state->exit_reason));
|
||
Assert(_vm_state == RUNNING);
|
||
|
||
_vm_exits ++;
|
||
|
||
_vm_state = NPT_EPT;
|
||
_blockade_emt.wakeup();
|
||
}
|
||
|
||
void _irq_window_pthread()
|
||
{
|
||
PVMCPU pVCpu = _vcpu;
|
||
|
||
Assert(_state->flags.value() & X86_EFL_IF);
|
||
Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
|
||
Assert(!(_state->inj_info.value() & IRQ_INJ_VALID_MASK));
|
||
|
||
Assert(_irq_win);
|
||
|
||
_irq_win = false;
|
||
|
||
/* request current tpr state from guest, it may block IRQs */
|
||
PDMApicSetTPR(pVCpu, _state->tpr_threshold.value());
|
||
|
||
if (!TRPMHasTrap(pVCpu)) {
|
||
|
||
bool res = VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
|
||
if (res)
|
||
Genode::log("NMI was set");
|
||
|
||
if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC |
|
||
VMCPU_FF_INTERRUPT_PIC))) {
|
||
|
||
uint8_t irq;
|
||
int rc = PDMGetInterrupt(pVCpu, &irq);
|
||
Assert(RT_SUCCESS(rc));
|
||
|
||
rc = TRPMAssertTrap(pVCpu, irq, TRPM_HARDWARE_INT);
|
||
Assert(RT_SUCCESS(rc));
|
||
}
|
||
|
||
if (!TRPMHasTrap(pVCpu)) {
|
||
_irq_drop++;
|
||
/* happens if PDMApicSetTPR (see above) mask IRQ */
|
||
_state->inj_info.charge(IRQ_INJ_NONE);
|
||
Genode::error("virq window pthread aaaaaaa while loop");
|
||
return;
|
||
}
|
||
}
|
||
_irq_inject++;
|
||
|
||
/*
|
||
* If we have no IRQ for injection, something with requesting the
|
||
* IRQ window went wrong. Probably it was forgotten to be reset.
|
||
*/
|
||
Assert(TRPMHasTrap(pVCpu));
|
||
|
||
/* interrupt can be dispatched */
|
||
uint8_t u8Vector;
|
||
TRPMEVENT enmType;
|
||
SVMEVENT Event;
|
||
RTGCUINT u32ErrorCode;
|
||
RTGCUINTPTR GCPtrFaultAddress;
|
||
uint8_t cbInstr;
|
||
|
||
Event.u = 0;
|
||
|
||
/* If a new event is pending, then dispatch it now. */
|
||
int rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0, 0);
|
||
AssertRC(rc);
|
||
Assert(enmType == TRPM_HARDWARE_INT);
|
||
Assert(u8Vector != X86_XCPT_NMI);
|
||
|
||
/* Clear the pending trap. */
|
||
rc = TRPMResetTrap(pVCpu);
|
||
AssertRC(rc);
|
||
|
||
Event.n.u8Vector = u8Vector;
|
||
Event.n.u1Valid = 1;
|
||
Event.n.u32ErrorCode = u32ErrorCode;
|
||
|
||
Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
|
||
|
||
_state->inj_info.charge(Event.u);
|
||
_state->inj_error.charge(Event.n.u32ErrorCode);
|
||
|
||
_last_inj_info = _state->inj_info.value();
|
||
_last_inj_error = _state->inj_error.value();
|
||
|
||
/*
|
||
Genode::log("type:info:vector ", Genode::Hex(Event.n.u3Type),
|
||
Genode::Hex(utcb->inj_info), Genode::Hex(u8Vector),
|
||
" intr:actv - ", Genode::Hex(utcb->intr_state),
|
||
Genode::Hex(utcb->actv_state), " mtd ",
|
||
Genode::Hex(utcb->mtd));
|
||
*/
|
||
}
|
||
|
||
|
||
inline bool continue_hw_accelerated(bool verbose = false)
|
||
{
|
||
uint32_t check_vm = VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST
|
||
| VM_FF_PGM_POOL_FLUSH_PENDING
|
||
| VM_FF_PDM_DMA;
|
||
uint32_t check_vcpu = VMCPU_FF_HM_TO_R3_MASK
|
||
| VMCPU_FF_PGM_SYNC_CR3
|
||
| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
|
||
| VMCPU_FF_REQUEST;
|
||
|
||
if (!VM_FF_IS_PENDING(_vm, check_vm) &&
|
||
!VMCPU_FF_IS_PENDING(_vcpu, check_vcpu))
|
||
return true;
|
||
|
||
Assert(!(VM_FF_IS_PENDING(_vm, VM_FF_PGM_NO_MEMORY)));
|
||
|
||
#define VERBOSE_VM(flag) \
|
||
do { \
|
||
if (VM_FF_IS_PENDING(_vm, flag)) \
|
||
Genode::log("flag ", flag, " pending"); \
|
||
} while (0)
|
||
|
||
#define VERBOSE_VMCPU(flag) \
|
||
do { \
|
||
if (VMCPU_FF_IS_PENDING(_vcpu, flag)) \
|
||
Genode::log("flag ", flag, " pending"); \
|
||
} while (0)
|
||
|
||
if (verbose) {
|
||
/*
|
||
* VM_FF_HM_TO_R3_MASK
|
||
*/
|
||
VERBOSE_VM(VM_FF_TM_VIRTUAL_SYNC);
|
||
VERBOSE_VM(VM_FF_PGM_NEED_HANDY_PAGES);
|
||
/* handled by the assertion above */
|
||
/* VERBOSE_VM(VM_FF_PGM_NO_MEMORY); */
|
||
VERBOSE_VM(VM_FF_PDM_QUEUES);
|
||
VERBOSE_VM(VM_FF_EMT_RENDEZVOUS);
|
||
|
||
VERBOSE_VM(VM_FF_REQUEST);
|
||
VERBOSE_VM(VM_FF_PGM_POOL_FLUSH_PENDING);
|
||
VERBOSE_VM(VM_FF_PDM_DMA);
|
||
|
||
/*
|
||
* VMCPU_FF_HM_TO_R3_MASK
|
||
*/
|
||
VERBOSE_VMCPU(VMCPU_FF_TO_R3);
|
||
/* when this flag gets set, a recall request follows */
|
||
/* VERBOSE_VMCPU(VMCPU_FF_TIMER); */
|
||
VERBOSE_VMCPU(VMCPU_FF_PDM_CRITSECT);
|
||
|
||
VERBOSE_VMCPU(VMCPU_FF_PGM_SYNC_CR3);
|
||
VERBOSE_VMCPU(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
|
||
VERBOSE_VMCPU(VMCPU_FF_REQUEST);
|
||
}
|
||
|
||
#undef VERBOSE_VMCPU
|
||
#undef VERBOSE_VM
|
||
|
||
return false;
|
||
}
|
||
|
||
virtual bool hw_load_state(Genode::Vcpu_state *, VM *, PVMCPU) = 0;
|
||
virtual bool hw_save_state(Genode::Vcpu_state *, VM *, PVMCPU) = 0;
|
||
virtual int vm_exit_requires_instruction_emulation(PCPUMCTX) = 0;
|
||
|
||
virtual void pause_vm() = 0;
|
||
virtual int attach_memory_to_vm(RTGCPHYS const,
|
||
RTGCUINT vbox_fault_reason) = 0;
|
||
|
||
public:
|
||
|
||
enum Exit_condition
|
||
{
|
||
SVM_NPT = 0xfc,
|
||
SVM_INVALID = 0xfd,
|
||
|
||
VCPU_STARTUP = 0xfe,
|
||
|
||
RECALL = 0xff,
|
||
};
|
||
|
||
|
||
Vcpu_handler(Genode::Env &env, size_t stack_size,
|
||
Genode::Affinity::Location location,
|
||
unsigned int cpu_id)
|
||
:
|
||
_ep(env, stack_size,
|
||
Genode::String<12>("EP-EMT-", cpu_id).string(), location),
|
||
_cpu_id(cpu_id)
|
||
{
|
||
pthread_mutexattr_t _attr;
|
||
pthread_mutexattr_init(&_attr);
|
||
|
||
pthread_cond_init(&_cond_wait, nullptr);
|
||
|
||
pthread_mutexattr_settype(&_attr, PTHREAD_MUTEX_ERRORCHECK);
|
||
pthread_mutex_init(&_mutex, &_attr);
|
||
}
|
||
|
||
unsigned int cpu_id() { return _cpu_id; }
|
||
|
||
|
||
void recall(PVM vm)
|
||
{
|
||
if (!_vm || !_vcpu) {
|
||
_vm = vm;
|
||
_vcpu = &vm->aCpus[_cpu_id];
|
||
}
|
||
|
||
if (_vm != vm || _vcpu != &vm->aCpus[_cpu_id])
|
||
Genode::error("wrong CPU !?");
|
||
|
||
_recall_req ++;
|
||
|
||
if (_irq_win) {
|
||
_recall_skip ++;
|
||
return;
|
||
}
|
||
|
||
asm volatile ("":::"memory");
|
||
|
||
if (_vm_state != PAUSED)
|
||
pause_vm();
|
||
|
||
_next_state = PAUSE_EXIT;
|
||
|
||
#if 0
|
||
if (_recall_req % 1000 == 0) {
|
||
using Genode::log;
|
||
|
||
while (other) {
|
||
log(other->_cpu_id, " exits=", other->_vm_exits,
|
||
" req:skip:drop,inv recall=", other->_recall_req, ":",
|
||
other->_recall_skip, ":", other->_recall_drop, ":",
|
||
other->_recall_inv, " req:inj:drop irq=",
|
||
other->_irq_request, ":", other->_irq_inject, ":",
|
||
other->_irq_drop);
|
||
|
||
other = other->next();
|
||
}
|
||
}
|
||
#endif
|
||
}
|
||
|
||
void halt(Genode::uint64_t const wait_ns)
|
||
{
|
||
/* calculate timeout */
|
||
timespec ts { 0, 0 };
|
||
clock_gettime(CLOCK_REALTIME, &ts);
|
||
ts = add_timespec_ns(ts, wait_ns);
|
||
|
||
/* wait for condition or timeout */
|
||
pthread_mutex_lock(&_mutex);
|
||
pthread_cond_timedwait(&_cond_wait, &_mutex, &ts);
|
||
pthread_mutex_unlock(&_mutex);
|
||
}
|
||
|
||
void wake_up()
|
||
{
|
||
pthread_mutex_lock(&_mutex);
|
||
pthread_cond_signal(&_cond_wait);
|
||
pthread_mutex_unlock(&_mutex);
|
||
}
|
||
|
||
int run_hw(PVMR0 pVMR0)
|
||
{
|
||
VM * pVM = reinterpret_cast<VM *>(pVMR0);
|
||
PVMCPU pVCpu = &pVM->aCpus[_cpu_id];
|
||
PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
||
|
||
if (!_vm || !_vcpu) {
|
||
_vm = pVM;
|
||
_vcpu = &pVM->aCpus[_cpu_id];
|
||
}
|
||
|
||
if (_vm != pVM || _vcpu != &pVM->aCpus[_cpu_id])
|
||
Genode::error("wrong CPU !?");
|
||
|
||
/* take the utcb state prepared during the last exit */
|
||
_state->ctrl_primary.charge(next_utcb.ctrl[0]);
|
||
_state->ctrl_secondary.charge(next_utcb.ctrl[1]);
|
||
|
||
/* Transfer vCPU state from vbox to Genode format */
|
||
if (!vbox_to_state(pVM, pVCpu) ||
|
||
!hw_load_state(_state, pVM, pVCpu)) {
|
||
|
||
Genode::error("loading vCPU state failed");
|
||
return VERR_INTERNAL_ERROR;
|
||
}
|
||
|
||
/* check whether to request interrupt window for injection */
|
||
_irq_win = check_to_request_irq_window(pVCpu);
|
||
|
||
/*
|
||
* Flag vCPU to be "pokeable" by external events such as interrupts
|
||
* from virtual devices. Only if this flag is set, the
|
||
* 'vmR3HaltGlobal1NotifyCpuFF' function calls 'SUPR3CallVMMR0Ex'
|
||
* with VMMR0_DO_GVMM_SCHED_POKE as argument to indicate such
|
||
* events. This function, in turn, will recall the vCPU.
|
||
*/
|
||
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
|
||
|
||
/* switch to hardware accelerated mode */
|
||
switch_to_hw(pCtx);
|
||
|
||
Assert(_state->actv_state.value() == ACTIVITY_STATE_ACTIVE);
|
||
|
||
/* see hmR0VmxExitToRing3 - sync recompiler state */
|
||
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR |
|
||
CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR |
|
||
CPUM_CHANGED_IDTR | CPUM_CHANGED_TR |
|
||
CPUM_CHANGED_HIDDEN_SEL_REGS |
|
||
CPUM_CHANGED_GLOBAL_TLB_FLUSH);
|
||
|
||
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
|
||
|
||
/* Transfer vCPU state from Genode to vbox format */
|
||
if (!state_to_vbox(pVM, pVCpu) ||
|
||
!hw_save_state(_state, pVM, pVCpu)) {
|
||
|
||
Genode::error("saving vCPU state failed");
|
||
return VERR_INTERNAL_ERROR;
|
||
}
|
||
|
||
#ifdef VBOX_WITH_REM
|
||
REMFlushTBs(pVM);
|
||
#endif
|
||
|
||
/* track guest mode changes - see VMM/VMMAll/IEMAllCImpl.cpp.h */
|
||
PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
|
||
|
||
int rc = vm_exit_requires_instruction_emulation(pCtx);
|
||
|
||
/* evaluated in VMM/include/EMHandleRCTmpl.h */
|
||
return rc;
|
||
}
|
||
};
|
||
|
||
#endif /* _VIRTUALBOX__VCPU_H_ */
|